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    Searched refs:ATOMIC_STORE (Results 1 - 21 of 21) sorted by relevancy

  /src/external/gpl3/gcc/dist/libgcc/config/pa/
sync-libfuncs.c 121 #define ATOMIC_STORE(TYPE, WIDTH) \
129 ATOMIC_STORE (u64, 8)
144 ATOMIC_STORE (u32, 4)
145 ATOMIC_STORE (u16, 2)
146 ATOMIC_STORE (u8, 1)
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 1102 /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val)
1104 ATOMIC_STORE,
SelectionDAGNodes.h 1383 N->getOpcode() == ISD::ATOMIC_STORE ||
1399 assert(((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) ||
1440 N->getOpcode() == ISD::ATOMIC_STORE;
  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
XCoreISelLowering.cpp 156 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
223 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op, DAG);
970 assert(N->getOpcode() == ISD::ATOMIC_STORE && "Bad Atomic OP");
999 // Because of how we convert atomic_load and atomic_store to normal loads and
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGDumper.cpp 100 case ISD::ATOMIC_STORE: return "AtomicStore";
LegalizeDAG.cpp 1029 case ISD::ATOMIC_STORE:
2760 case ISD::ATOMIC_STORE: {
LegalizeIntegerTypes.cpp 1483 case ISD::ATOMIC_STORE:
4217 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
SelectionDAG.cpp 728 case ISD::ATOMIC_STORE: {
7085 Opcode == ISD::ATOMIC_STORE) &&
7090 SDVTList VTs = Opcode == ISD::ATOMIC_STORE ? getVTList(MVT::Other) :
SelectionDAGBuilder.cpp 4745 SDValue OutChain = DAG.getAtomic(ISD::ATOMIC_STORE, dl, MemVT, InChain,
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyRuntimeLibcallSignatures.cpp 426 Table[RTLIB::ATOMIC_STORE] = unsupported;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelLowering.cpp 1603 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1609 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom);
3066 case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
AtomicExpandPass.cpp 1529 RTLIB::ATOMIC_STORE, RTLIB::ATOMIC_STORE_1, RTLIB::ATOMIC_STORE_2,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600ISelLowering.cpp 241 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
SIISelLowering.cpp 830 setTargetDAGCombine(ISD::ATOMIC_STORE);
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXISelDAGToDAG.cpp 91 case ISD::ATOMIC_STORE:
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 189 // Lower ATOMIC_LOAD and ATOMIC_STORE into normal volatile loads and
192 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
252 setOperationAction(ISD::ATOMIC_STORE, MVT::i128, Custom);
4071 // Because of how we convert atomic_load and atomic_store to normal loads and
5429 case ISD::ATOMIC_STORE:
5529 case ISD::ATOMIC_STORE: {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelDAGToDAG.cpp 817 Use->getOpcode() != ISD::ATOMIC_STORE)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.cpp 469 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 1324 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1328 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
9936 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 1280 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 509 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
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