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    Searched refs:AUX_CONTROL (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_aux.c 118 value = REG_READ(AUX_CONTROL);
120 AUX_CONTROL,
127 AUX_CONTROL,
135 AUX_CONTROL,
139 REG_WRITE(AUX_CONTROL, value);
144 REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1,
150 AUX_CONTROL,
153 REG_WRITE(AUX_CONTROL, value);
155 REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0,
dce_aux.h 36 SRI(AUX_CONTROL, DP_AUX, id), \
45 SRI(AUX_CONTROL, DP_AUX, id), \
55 uint32_t AUX_CONTROL;
95 AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\
118 AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\
119 AUX_SF(AUX_CONTROL, AUX_RESET, mask_sh),\
120 AUX_SF(AUX_CONTROL, AUX_RESET_DONE, mask_sh),\
271 uint32_t aux_control; member in struct:aux_engine_dce110::__anonfdd657540208
dce_link_encoder.h 42 SRI(AUX_CONTROL, DP_AUX, id), \
110 uint32_t AUX_CONTROL;
amdgpu_dce_link_encoder.c 502 uint32_t addr = AUX_REG(AUX_CONTROL);
505 set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL);
506 set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN);
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_dp_auxch.c 109 tmp = RREG32(AUX_CONTROL + aux_offset[instance]);
115 WREG32(AUX_CONTROL + aux_offset[instance], tmp);
nid.h 828 #define AUX_CONTROL 0x6200
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
dcn10_link_encoder.h 38 SRI(AUX_CONTROL, DP_AUX, id), \
75 uint32_t AUX_CONTROL;
amdgpu_dcn10_link_encoder.c 1398 AUX_REG_UPDATE_2(AUX_CONTROL,

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