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Searched refs:A_IMR_CPU0_BASE (Results 1 - 4 of 4) sorted by relevancy

/src/sys/arch/mips/sibyte/dev/
sbscd.c	`61 { A_IMR_CPU0_BASE,`
/src/sys/arch/evbmips/sbmips/
sb1250_icu.c	`275 vaddr_t imr = MIPS_PHYS_TO_KSEG1(A_IMR_CPU0_BASE + R_IMR_INTERRUPT_MASK); 280 WRITE_REG(MIPS_PHYS_TO_KSEG1(A_IMR_CPU0_BASE + R_IMR_INTERRUPT_MASK),`
/src/sys/arch/sbmips/sbmips/
sb1250_icu.c	`275 vaddr_t imr = MIPS_PHYS_TO_KSEG1(A_IMR_CPU0_BASE + R_IMR_INTERRUPT_MASK); 280 WRITE_REG(MIPS_PHYS_TO_KSEG1(A_IMR_CPU0_BASE + R_IMR_INTERRUPT_MASK),`
/src/sys/arch/mips/sibyte/include/
sb1250_regs.h	`718 #define A_IMR_CPU0_BASE 0x0010020000 723 #define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)IMR_REGISTER_SPACING) 750 (A_IMR_CPU0_BASE + (cpu IMR_REGISTER_SPACING) + reg)`

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