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    Searched refs:AddC (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineAndOrXor.cpp 1880 const APInt *AddC;
1881 if (match(Op0, m_Add(m_Value(X), m_APInt(AddC)))) {
1883 // (X + AddC) & LowMaskC --> X & LowMaskC
1886 if ((*AddC & LowMask).isNullValue())
1893 if (Op0->hasOneUse() && C->isPowerOf2() && (*AddC & (*C - 1)) == 0) {
1894 assert((*C & *AddC) != 0 && "Expected common bit");
2520 ConstantInt *AddC;
2521 if (match(LHS0, m_Add(m_Specific(RHS0), m_ConstantInt(AddC))))
2522 if (RHSC->getValue() + AddC->getValue() == LHSC->getValue())
InstCombineAddSub.cpp 2094 // sub (X + AddC), (X & AndC) --> and (X + AddC), ~AndC
2095 const APInt *AddC, *AndC;
2096 if (match(Op0, m_Add(m_Value(X), m_APInt(AddC))) &&
2099 unsigned Cttz = AddC->countTrailingZeros();
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
CodeGenPrepare.cpp 1543 const APInt *CmpC, *AddC;
1544 if (match(U, m_Add(m_Specific(A), m_APInt(AddC))) &&
1545 match(B, m_APInt(CmpC)) && *AddC == -(*CmpC)) {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 1615 case ISD::ADDC: return visitADDC(N);
2729 return DAG.getNode(ISD::ADDC, DL, N->getVTList(), N1, N0);
2731 // fold (addc x, 0) -> x + no carry out
2869 // fold (adde x, y, false) -> (addc x, y)
2871 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
5115 APInt ADDC = ADDI->getAPIntValue();
5117 if (ADDC.getMinSignedBits() <= 64 &&
5119 !TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
5123 ADDC |= Mask;
5124 if (TLI.isLegalAddImmediate(ADDC.getSExtValue()))
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