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    Searched refs:AddOp (Results 1 - 10 of 10) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
XCoreISelLowering.cpp 585 SDValue AddOp;
588 AddOp = N0;
591 AddOp = N1;
596 if (requireIntermediatesHaveOneUse && !AddOp.hasOneUse())
604 Addend0 = AddOp.getOperand(0);
605 Addend1 = AddOp.getOperand(1);
608 if (AddOp.getOperand(0).getOpcode() == ISD::MUL) {
610 if (requireIntermediatesHaveOneUse && !AddOp.getOperand(0).hasOneUse())
612 Mul0 = AddOp.getOperand(0).getOperand(0);
613 Mul1 = AddOp.getOperand(0).getOperand(1)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/TableGen/
SetTheory.cpp 39 struct AddOp : public SetTheory::Operator {
258 addOperator("add", std::make_unique<AddOp>());
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineSelect.cpp 1730 Instruction *AddOp = nullptr, *SubOp = nullptr;
1735 AddOp = FI;
1741 AddOp = TI;
1745 if (AddOp) {
1747 if (SubOp->getOperand(0) == AddOp->getOperand(0)) {
1748 OtherAddOp = AddOp->getOperand(1);
1749 } else if (SubOp->getOperand(0) == AddOp->getOperand(1)) {
1750 OtherAddOp = AddOp->getOperand(0);
1760 FastMathFlags Flags = AddOp->getFastMathFlags();
1770 if (AddOp != TI
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/
LoopVectorize.cpp 2279 Instruction::BinaryOps AddOp;
2282 AddOp = Instruction::Add;
2285 AddOp = II.getInductionOpcode();
2325 Builder.CreateBinOp(AddOp, LastInduction, SplatVF, "step.add"));
2564 Instruction::BinaryOps AddOp;
2567 AddOp = Instruction::Add;
2570 AddOp = ID.getInductionOpcode();
2602 auto *Add = Builder.CreateBinOp(AddOp, SplatIV, Mul);
2616 AddOp, StartIdx0, getSignedIntOrFpConstant(ScalarIVTy, Lane));
2623 auto *Add = Builder.CreateBinOp(AddOp, ScalarIV, Mul)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelDAGToDAG.cpp 1703 unsigned AddOp = AMDGPU::V_ADD_CO_U32_e32;
1705 AddOp = AMDGPU::V_ADD_U32_e64;
1708 Addr = SDValue(CurDAG->getMachineNode(AddOp, DL, MVT::i32, Opnds), 0);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonInstrInfo.cpp 1968 const MachineOperand &AddOp = MI.getOperand(2);
1969 if (AddOp.isImm()) {
1970 Value = AddOp.getImm();
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
ScalarEvolution.cpp 2536 for (unsigned AddOp = 0, e = Ops.size(); AddOp != e; ++AddOp)
2537 if (MulOpSCEV == Ops[AddOp]) {
2553 if (AddOp < Idx) {
2554 Ops.erase(Ops.begin()+AddOp);
2558 Ops.erase(Ops.begin()+AddOp-1);
2913 for (const SCEV *AddOp : Add->operands()) {
2914 const SCEV *Mul = getMulExpr(Ops[0], AddOp, SCEV::FlagAnyWrap,
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 856 Register &MulOp2, Register &AddOp,
861 GetOperandInfo(Instr.getOperand(AddOpIdx), AddOp, AddOpKillFlag);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeIntegerTypes.cpp 835 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB;
841 DAG.getNode(AddOp, dl, PromotedType, Op1Promoted, Op2Promoted);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp     [all...]

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