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    Searched refs:AddSub (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86BaseInfo.h 120 AddSub,
268 return FirstMacroFusionInstKind::AddSub;
345 case X86::FirstMacroFusionInstKind::AddSub:
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 714 ARM_AM::AddrOpc AddSub = ARM_AM::add;
716 AddSub = ARM_AM::sub;
722 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
745 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
808 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
819 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
844 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
855 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
859 if (AddSub == ARM_AM::sub) Val *= -1;
875 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC
    [all...]
ARMLoadStoreOptimizer.cpp 1519 ARM_AM::AddrOpc AddSub = Offset < 0 ? ARM_AM::sub : ARM_AM::add;
1553 int Imm = ARM_AM::getAM2Opc(AddSub, abs(Offset), ARM_AM::no_shift);
1583 int Imm = ARM_AM::getAM2Opc(AddSub, abs(Offset), ARM_AM::no_shift);
2307 ARM_AM::AddrOpc AddSub = ARM_AM::add;
2309 AddSub = ARM_AM::sub;
2315 Offset = ARM_AM::getAM3Opc(AddSub, OffImm);
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineSelect.cpp 2192 BinaryOperator *AddSub;
2195 if (!match(MinMax2, m_SMax(m_BinOp(AddSub), m_APInt(MinValue))))
2199 if (!match(MinMax2, m_SMin(m_BinOp(AddSub), m_APInt(MaxValue))))
2217 if (MinMax2->hasNUsesOrMore(3) || AddSub->hasNUsesOrMore(3))
2224 if(!match(AddSub, m_BinOp(m_SExt(m_Value(A)), m_SExt(m_Value(B)))))
2234 if (AddSub->getOpcode() == Instruction::Add)
2236 else if (AddSub->getOpcode() == Instruction::Sub)
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 2952 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2958 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2977 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2981 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
3005 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
3011 Val = ARM_AM::getAM3Opc(AddSub, Val);
3037 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
3041 Val = ARM_AM::getAM3Opc(AddSub, Val);
3063 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
3069 Val = ARM_AM::getAM5Opc(AddSub, Val)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 9442 /// the result of ADDSUB/SUBADD operation.
9443 /// If true is returned then the operands of ADDSUB = Opnd0 +- Opnd1
9534 // different. Don't try to fold this build_vector into an ADDSUB/SUBADD if the
9548 /// recognized as ADDSUB/SUBADD(\p Opnd0, \p Opnd1) into
9553 /// SDNode that potentially can be replaced with an X86ISD::ADDSUB operation
9555 /// before replacement of such SDNode with ADDSUB operation. Thus the number
9561 /// %Addsub = shufflevector <2 x double> %Sub, <2 x double> %Add,
9563 /// There is a def for %Addsub here, which potentially can be replaced by
9564 /// X86ISD::ADDSUB operation:
9565 /// %Addsub = X86ISD::ADDSUB %AB, %
    [all...]

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