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Searched
refs:AddrBaseReg
(Results
1 - 17
of
17
) sorted by relevancy
/src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InsertPrefetch.cpp
82
Register BaseReg = MI.getOperand(Op + X86::
AddrBaseReg
).getReg();
217
static_assert(X86::
AddrBaseReg
== 0 && X86::AddrScaleAmt == 1 &&
225
MIB.addReg(Current->getOperand(MemOpOffset + X86::
AddrBaseReg
).getReg())
X86OptimizeLEAs.cpp
194
return MemOpKey(&MI.getOperand(N + X86::
AddrBaseReg
),
365
if (TII->getRegClass(Desc, MemOpNo + X86::
AddrBaseReg
, TRI, *MF) !=
460
if (!isIdenticalOp(MI.getOperand(MemOpNo + X86::
AddrBaseReg
), MO))
466
if (i != (unsigned)(MemOpNo + X86::
AddrBaseReg
) &&
561
MI.getOperand(MemOpNo + X86::
AddrBaseReg
)
X86AsmPrinter.cpp
288
const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::
AddrBaseReg
);
325
PrintModifiedOperand(MI, OpNo + X86::
AddrBaseReg
, O, Modifier);
353
const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::
AddrBaseReg
);
375
PrintOperand(MI, OpNo + X86::
AddrBaseReg
, O);
X86CallFrameOptimization.cpp
422
// Note that
AddrBaseReg
may, counter to its name, not be a register,
427
if (!I->getOperand(X86::
AddrBaseReg
).isReg() ||
428
(I->getOperand(X86::
AddrBaseReg
).getReg() != StackPtr) ||
X86FixupLEAs.cpp
372
const MachineOperand &Base = MI.getOperand(1 + X86::
AddrBaseReg
);
467
MachineOperand &p = MI.getOperand(AddrOffset + X86::
AddrBaseReg
);
504
const MachineOperand &Base = MI.getOperand(1 + X86::
AddrBaseReg
);
556
const MachineOperand &Base = MI.getOperand(1 + X86::
AddrBaseReg
);
X86InstrInfo.h
114
MI.getOperand(Op + X86::
AddrBaseReg
).isReg() &&
X86SpeculativeLoadHardening.cpp
1338
MI.getOperand(MemRefBeginIdx + X86::
AddrBaseReg
);
1412
MI.getOperand(MemRefBeginIdx + X86::
AddrBaseReg
);
1814
UseMI.getOperand(MemRefBeginIdx + X86::
AddrBaseReg
);
X86AvoidStoreForwardingBlocks.cpp
301
return MI->getOperand(AddrOffset + X86::
AddrBaseReg
);
X86LoadValueInjectionLoadHardening.cpp
787
MI.getOperand(MemRefBeginIdx + X86::
AddrBaseReg
);
X86InstrInfo.cpp
679
if (MI.getOperand(Op + X86::
AddrBaseReg
).isFI() &&
686
FrameIndex = MI.getOperand(Op + X86::
AddrBaseReg
).getIndex();
1085
if (MI.getOperand(1 + X86::
AddrBaseReg
).isReg() &&
1090
Register BaseReg = MI.getOperand(1 + X86::
AddrBaseReg
).getReg();
1110
if (!MI.getOperand(1 + X86::
AddrBaseReg
).isReg())
1112
Register BaseReg = MI.getOperand(1 + X86::
AddrBaseReg
).getReg();
3678
auto &BaseOp = MemI.getOperand(MemRefBegin + X86::
AddrBaseReg
);
3747
&MemOp.getOperand(MemRefBegin + X86::
AddrBaseReg
);
6727
if (!HasSameOp(X86::
AddrBaseReg
) || !HasSameOp(X86::AddrScaleAmt) ||
X86MCInstLower.cpp
382
Inst.getOperand(AddrBase + X86::
AddrBaseReg
).isReg() &&
406
(Inst.getOperand(AddrBase + X86::
AddrBaseReg
).getReg() != 0 ||
/src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86MCCodeEmitter.cpp
163
const MCOperand &Base = MI.getOperand(Op + X86::
AddrBaseReg
);
183
const MCOperand &BaseReg = MI.getOperand(Op + X86::
AddrBaseReg
);
205
const MCOperand &BaseReg = MI.getOperand(Op + X86::
AddrBaseReg
);
386
const MCOperand &Base = MI.getOperand(Op + X86::
AddrBaseReg
);
901
unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::
AddrBaseReg
);
948
unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::
AddrBaseReg
);
964
unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::
AddrBaseReg
);
981
unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::
AddrBaseReg
);
1008
unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::
AddrBaseReg
);
1261
REX |= isREXExtendedReg(MI, MemOperand + X86::
AddrBaseReg
) << 0; // REX.
[
all
...]
X86ATTInstPrinter.cpp
398
const MCOperand &BaseReg = MI->getOperand(Op + X86::
AddrBaseReg
);
419
printOperand(MI, Op + X86::
AddrBaseReg
, O);
X86IntelInstPrinter.cpp
355
const MCOperand &BaseReg = MI->getOperand(Op+X86::
AddrBaseReg
);
367
printOperand(MI, Op+X86::
AddrBaseReg
, O);
X86AsmBackend.cpp
349
unsigned BaseRegNum = MemoryOperand + CurOp + X86::
AddrBaseReg
;
425
unsigned BaseRegNum = MemoryOperand + X86::
AddrBaseReg
;
X86BaseInfo.h
32
AddrBaseReg
= 0,
X86MCTargetDesc.cpp
543
const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::
AddrBaseReg
);
Completed in 34 milliseconds
Indexes created Mon Sep 28 00:25:45 UTC 2026