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    Searched refs:AddrIdx (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
MipsMCNaCl.h 20 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
MipsNaClELFStreamer.cpp 124 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx,
130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg();
157 unsigned AddrIdx = 0;
159 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx,
164 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx)
170 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter);
210 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
231 *AddrIdx = 1;
242 *AddrIdx = 1;
250 *AddrIdx = 2
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SILoadStoreOptimizer.cpp 109 int AddrIdx[MaxAddressRegs];
116 const MachineOperand &AddrRegNext = MI.getOperand(AddrIdx[i]);
540 AddrIdx[NumAddresses++] =
543 AddrIdx[NumAddresses++] =
546 AddrIdx[NumAddresses++] =
549 AddrIdx[NumAddresses++] =
552 AddrIdx[NumAddresses++] =
555 AddrIdx[NumAddresses++] =
558 AddrIdx[NumAddresses++] =
563 AddrReg[J] = &I->getOperand(AddrIdx[J])
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsDelaySlotFiller.cpp 738 unsigned AddrIdx;
739 if ((isBasePlusOffsetMemoryAccess(CurrI->getOpcode(), &AddrIdx) &&
740 baseRegNeedsLoadStoreMask(CurrI->getOperand(AddrIdx).getReg())) ||

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