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    Searched refs:AddrReg (Results 1 - 23 of 23) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
ARCExpandPseudos.cpp 62 unsigned AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass);
65 BuildMI(*SI.getParent(), SI, SI.getDebugLoc(), TII->get(AddOpc), AddrReg)
71 .addReg(AddrReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
MipsNaClELFStreamer.cpp 101 void emitMask(unsigned AddrReg, unsigned MaskReg,
105 MaskInst.addOperand(MCOperand::createReg(AddrReg));
106 MaskInst.addOperand(MCOperand::createReg(AddrReg));
114 unsigned AddrReg = MI.getOperand(0).getReg();
117 emitMask(AddrReg, IndirectBranchMaskReg, STI);
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVExpandAtomicPseudoInsts.cpp 223 Register AddrReg = MI.getOperand(2).getReg();
234 .addReg(AddrReg);
248 .addReg(AddrReg)
285 Register AddrReg = MI.getOperand(2).getReg();
300 .addReg(AddrReg);
333 .addReg(AddrReg)
425 Register AddrReg = MI.getOperand(3).getReg();
440 .addReg(AddrReg);
492 .addReg(AddrReg)
537 Register AddrReg = MI.getOperand(2).getReg()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600InstrInfo.cpp 1103 unsigned AddrReg;
1106 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break;
1107 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break;
1108 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break;
1109 case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(Address); break;
1116 AddrReg, ValueReg)
1135 unsigned AddrReg;
1138 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break;
1139 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break;
1140 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break
    [all...]
SILoadStoreOptimizer.cpp 110 const MachineOperand *AddrReg[MaxAddressRegs];
118 if (AddrReg[i]->isImm() || AddrRegNext.isImm()) {
119 if (AddrReg[i]->isImm() != AddrRegNext.isImm() ||
120 AddrReg[i]->getImm() != AddrRegNext.getImm()) {
128 if (AddrReg[i]->getReg() != AddrRegNext.getReg() ||
129 AddrReg[i]->getSubReg() != AddrRegNext.getSubReg()) {
138 const MachineOperand *AddrOp = AddrReg[i];
563 AddrReg[J] = &I->getOperand(AddrIdx[J]);
1054 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr);
1083 Register BaseReg = AddrReg->getReg()
    [all...]
AMDGPUCallLowering.cpp 99 auto AddrReg = MIRBuilder.buildFrameIndex(
102 return AddrReg.getReg(0);
205 auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg);
207 return AddrReg.getReg(0);
AMDGPULegalizerInfo.cpp 4028 Register AddrReg = SrcOp.getReg();
4031 AddrReg = B.buildBitcast(V2S16, AddrReg).getReg(0);
4032 PackedAddrs.push_back(AddrReg);
4036 PackedAddrs.push_back(AddrReg);
4049 B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)})
4054 V2S16, {AddrReg, MI.getOperand(ArgOffset + I + 1).getReg()})
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64SIMDInstrOpt.cpp 507 unsigned SeqReg, AddrReg;
521 AddrReg = MI.getOperand(1).getReg();
575 .addReg(AddrReg)
615 .addReg(AddrReg)
620 .addReg(AddrReg)
AArch64ExpandPseudoInsts.cpp 196 Register AddrReg = MI.getOperand(2).getReg();
218 .addReg(AddrReg);
235 .addReg(AddrReg);
276 Register AddrReg = MI.getOperand(3).getReg();
299 .addReg(AddrReg);
328 .addReg(AddrReg);
AArch64FastISel.cpp 229 bool emitStoreRelease(MVT VT, unsigned SrcReg, unsigned AddrReg,
2037 unsigned AddrReg,
2050 AddrReg = constrainOperandRegClass(II, AddrReg, 1);
2053 .addReg(AddrReg)
2177 unsigned AddrReg = getRegForValue(PtrV);
2178 return emitStoreRelease(VT, SrcReg, AddrReg,
2496 unsigned AddrReg = getRegForValue(BI->getOperand(0));
2497 if (AddrReg == 0)
2502 AddrReg = constrainOperandRegClass(II, AddrReg, II.getNumDefs())
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86CallLowering.cpp 101 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
104 return AddrReg.getReg(0);
X86SpeculativeLoadHardening.cpp 1162 Register AddrReg = MRI->createVirtualRegister(&X86::GR64RegClass);
1164 BuildMI(MBB, InsertPt, DebugLoc(), TII->get(X86::LEA64r), AddrReg)
1175 .addReg(AddrReg, RegState::Kill);
X86InstructionSelector.cpp 1409 Register AddrReg = MRI.createVirtualRegister(&X86::GR64RegClass);
1410 BuildMI(*I.getParent(), I, DbgLoc, TII.get(X86::MOV64ri), AddrReg)
1419 AddrReg)
X86FastISel.cpp 3775 Register AddrReg = createResultReg(&X86::GR64RegClass);
3777 AddrReg)
3781 addRegReg(MIB, AddrReg, false, PICBase, false);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMCallLowering.cpp 105 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
108 return AddrReg.getReg(0);
ARMExpandPseudoInsts.cpp 1592 Register AddrReg = MI.getOperand(2).getReg();
1630 MIB.addReg(AddrReg);
1654 .addReg(AddrReg);
1720 Register AddrReg = MI.getOperand(2).getReg();
1748 MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
1777 MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
ARMFastISel.cpp 1318 unsigned AddrReg = getRegForValue(I->getOperand(0));
1319 if (AddrReg == 0) return false;
1325 TII.get(Opc)).addReg(AddrReg));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64CallLowering.cpp 145 auto AddrReg = MIRBuilder.buildFrameIndex(LLT::pointer(0, 64), FI);
146 return AddrReg.getReg(0);
257 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
260 return AddrReg.getReg(0);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsCallLowering.cpp 271 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
280 return AddrReg.getReg(0);
MipsISelLowering.cpp 2546 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
2548 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2551 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCFastISel.cpp 1859 unsigned AddrReg = getRegForValue(I->getOperand(0));
1860 if (AddrReg == 0)
1864 .addReg(AddrReg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
AArch64InstPrinter.cpp 741 unsigned AddrReg = MI->getOperand(OpNum++).getReg();
742 O << ", [" << getRegisterName(AddrReg) << ']';
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 3868 Register AddrReg = MI.getOperand(1).getReg();
3894 LLT PtrTy = MRI.getType(AddrReg);
3913 MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset);

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