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    Searched refs:AlignMask (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonOptAddrMode.cpp 325 unsigned AlignMask = 0;
328 AlignMask = 0x7;
331 AlignMask = 0x3;
334 AlignMask = 0x1;
337 AlignMask = 0x0;
343 if ((AlignMask & Offset) != 0)
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMFrameLowering.cpp 363 const unsigned AlignMask = Alignment.value() - 1U;
379 .addImm(~AlignMask)
381 } else if (AlignMask <= 255) {
384 .addImm(AlignMask)
409 .addImm(~AlignMask)
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/AsmPrinter/
DwarfUnit.cpp 1583 uint32_t AlignMask = ~(AlignInBits - 1);
1585 uint64_t StartBitOffset = Offset - (Offset & AlignMask);
1590 uint64_t HiMark = (Offset + FieldSize) & AlignMask;
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kISelLowering.cpp 1145 uint64_t AlignMask = StackAlignment - 1;
1148 if ((Offset & AlignMask) <= (StackAlignment - SlotSize)) {
1150 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1154 ((~AlignMask) & Offset) + StackAlignment + (StackAlignment - SlotSize);
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineCalls.cpp 1744 uint64_t AlignMask;
1747 m_Cmp(Pred, m_And(m_Value(A), m_ConstantInt(AlignMask)),
1750 if (isPowerOf2_64(AlignMask + 1)) {
1759 (unsigned)MinAlign(Offset, AlignMask + 1), A};
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 6364 APInt AlignMask(IntPtrTy.getSizeInBits(), Alignment.value(), true);
6365 AlignMask.negate();
6366 auto AlignCst = MIRBuilder.buildConstant(IntPtrTy, AlignMask);

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