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    Searched refs:AllocateReg (Results 1 - 17 of 17) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCCallingConv.cpp 49 State.AllocateReg(ArgRegs[RegNum]);
74 State.AllocateReg(ArgRegs[RegNum + i]);
98 State.AllocateReg(ArgRegs[RegNum]);
118 unsigned Reg = State.AllocateReg(HiRegList);
127 unsigned T = State.AllocateReg(LoRegList[i]);
147 unsigned Reg = State.AllocateReg(HiRegList, LoRegList);
PPCISelLowering.cpp 6560 if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32))
6587 if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32))
6602 unsigned FReg = State.AllocateReg(FPR);
6608 if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) {
6648 if (unsigned VReg = State.AllocateReg(VR)) {
6669 unsigned Reg = State.AllocateReg(GPRs);
6681 if (unsigned VReg = State.AllocateReg(VR)) {
6685 State.AllocateReg(GPRs);
6710 const unsigned FirstReg = State.AllocateReg(PPC::R9);
6711 const unsigned SecondReg = State.AllocateReg(PPC::R10)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZCallingConv.h 121 Reg = State.AllocateReg(SystemZ::ELFArgGPRs);
123 Reg = State.AllocateReg(SystemZ::XPLINK64ArgGPRs);
147 State.AllocateReg(SystemZ::XPLINK64ArgGPRs);
151 State.AllocateReg(SystemZ::XPLINK64ArgGPRs);
152 State.AllocateReg(SystemZ::XPLINK64ArgGPRs);
159 State.AllocateReg(SystemZ::XPLINK64ArgFPRs[I + 1]);
182 State.AllocateReg(SystemZ::R1D);
184 bool AllocGPR2 = State.AllocateReg(SystemZ::R2D);
185 bool AllocGPR3 = State.AllocateReg(SystemZ::R3D);
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kCallingConv.h 65 IsPtr ? State.AllocateReg(AddrRegList) : State.AllocateReg(DataRegList);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86CallingConv.cpp 53 unsigned Reg = State.AllocateReg(AvailableRegs[I]);
104 unsigned AssigedReg = State.AllocateReg(Reg);
149 (void)State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT));
157 (void)State.AllocateReg(CC_X86_64_VectorCallGetGPRs());
160 if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) {
211 if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) {
261 if (unsigned Reg = State.AllocateReg(RegList)) {
282 It.convertToReg(State.AllocateReg(RegList[FirstFree++]));
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMCallingConv.cpp 27 if (unsigned Reg = State.AllocateReg(RegList))
41 if (unsigned Reg = State.AllocateReg(RegList))
70 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList);
74 Reg = State.AllocateReg(GPRArgRegs);
92 unsigned T = State.AllocateReg(LoRegList[i]);
119 unsigned Reg = State.AllocateReg(HiRegList, LoRegList);
207 State.AllocateReg(RegList[RegIdx++]);
253 It.convertToReg(State.AllocateReg(RegList[RegIdx++]));
266 State.AllocateReg(Reg);
291 unsigned Reg = State.AllocateReg(RegList)
    [all...]
ARMISelLowering.cpp 2688 unsigned Reg = State->AllocateReg(GPRArgRegs);
2695 Reg = State->AllocateReg(GPRArgRegs);
2708 while (State->AllocateReg(GPRArgRegs))
2725 State->AllocateReg(GPRArgRegs);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
CallingConvLower.h 348 /// AllocateReg - Attempt to allocate one register. If it is not available,
351 MCRegister AllocateReg(MCPhysReg Reg) {
358 /// Version of AllocateReg with extra register to be shadowed.
359 MCRegister AllocateReg(MCPhysReg Reg, MCPhysReg ShadowReg) {
367 /// AllocateReg - Attempt to allocate one of the specified registers. If none
370 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) {
410 /// Version of AllocateReg with list of registers to be shadowed.
411 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) {
437 /// Note that, unlike AllocateReg, this shadows ALL of the shadow registers.
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64CallingConvention.cpp 65 State.AllocateReg(ZRegList[I]);
192 State.AllocateReg(Reg);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUCallLowering.cpp 445 CCInfo.AllocateReg(PrivateSegmentBufferReg);
451 CCInfo.AllocateReg(DispatchPtrReg);
457 CCInfo.AllocateReg(QueuePtrReg);
468 CCInfo.AllocateReg(InputPtrReg);
474 CCInfo.AllocateReg(DispatchIDReg);
480 CCInfo.AllocateReg(FlatScratchInitReg);
604 CCInfo.AllocateReg(ImplicitBufferPtrReg);
677 CCInfo.AllocateReg(AMDGPU::VGPR0);
678 CCInfo.AllocateReg(AMDGPU::VGPR1);
733 CCInfo.AllocateReg(Info->getScratchRSrcReg())
    [all...]
SIISelLowering.cpp 1834 CCInfo.AllocateReg(Reg);
1849 CCInfo.AllocateReg(Reg);
1863 CCInfo.AllocateReg(Reg);
1889 Reg = CCInfo.AllocateReg(Reg);
1907 Reg = CCInfo.AllocateReg(Reg);
1921 Reg = CCInfo.AllocateReg(Reg);
1969 Register Reg = CCInfo.AllocateReg(AMDGPU::VGPR31);
2022 CCInfo.AllocateReg(ImplicitBufferPtrReg);
2029 CCInfo.AllocateReg(PrivateSegmentBufferReg);
2035 CCInfo.AllocateReg(DispatchPtrReg)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.cpp 2910 Reg = State.AllocateReg(FloatVectorIntRegs);
2912 State.AllocateReg(Mips::A1);
2914 State.AllocateReg(Mips::A3);
2918 Reg = State.AllocateReg(IntRegs);
2922 Reg = State.AllocateReg(IntRegs);
2926 Reg = State.AllocateReg(IntRegs);
2931 Reg = State.AllocateReg(IntRegs);
2933 Reg = State.AllocateReg(IntRegs);
2934 State.AllocateReg(IntRegs);
2939 Reg = State.AllocateReg(F32Regs)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRISelLowering.cpp 1058 Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
1060 Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
1111 Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
1113 Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 6640 if (Register Reg = State.AllocateReg(ArgGPRs)) {
6658 if (Register Reg = State.AllocateReg(ArgGPRs)) {
6742 State.AllocateReg(ArgGPRs);
6761 Register Reg = State.AllocateReg(ArgGPRs);
6769 if (!State.AllocateReg(ArgGPRs))
6811 Reg = State.AllocateReg(ArgFPR16s);
6813 Reg = State.AllocateReg(ArgFPR32s);
6815 Reg = State.AllocateReg(ArgFPR64s);
6824 Reg = State.AllocateReg(RISCV::V0);
6826 Reg = State.AllocateReg(ArgVRs)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430ISelLowering.cpp 529 unsigned Reg = State.AllocateReg(RegList);
537 unsigned Reg = State.AllocateReg(RegList);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelLowering.cpp 62 if (Register Reg = State.AllocateReg(RegList)) {
72 if (Register Reg = State.AllocateReg(RegList))
89 if (Register Reg = State.AllocateReg(RegList))
95 if (Register Reg = State.AllocateReg(RegList))
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 149 State.AllocateReg(ArgRegs[RegNum]);

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