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    Searched refs:AmtTy (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64LegalizerInfo.cpp 126 const auto &AmtTy = Query.Types[1];
128 AmtTy.getSizeInBits() == 32;
790 LLT AmtTy = MRI.getType(AmtReg);
791 (void)AmtTy;
792 assert(AmtTy.isScalar() && "Expected a scalar rotate");
793 assert(AmtTy.getSizeInBits() < 64 && "Expected this rotate to be legal");
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 4350 const LLT HalfTy, const LLT AmtTy) {
4373 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
4378 Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt));
4380 MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt));
4382 NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
4390 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
4396 auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
4400 NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
4408 NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
4411 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits))
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CombinerHelper.cpp 3928 LLT AmtTy = MRI.getType(Amt);
3929 auto Bits = Builder.buildConstant(AmtTy, Bitsize);
3930 Amt = Builder.buildURem(AmtTy, MI.getOperand(2).getReg(), Bits).getReg(0);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 24839 MVT AmtTy = ShAmt.getSimpleValueType() == MVT::i8 ? MVT::v16i8 : MVT::v8i16;
24840 ShAmt = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(ShAmt), AmtTy, ShAmt);
24846 (128 - AmtTy.getScalarSizeInBits()) / 8, SDLoc(ShAmt), MVT::i8);
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