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    Searched refs:AmtVT (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstCombineIntrinsic.cpp 204 auto AmtVT = Amt->getType();
212 assert(AmtVT->isIntegerTy(32) && "Unexpected shift-by-immediate type");
231 assert(AmtVT->isVectorTy() && AmtVT->getPrimitiveSizeInBits() == 128 &&
232 cast<VectorType>(AmtVT)->getElementType() == SVT &&
234 unsigned NumAmtElts = cast<FixedVectorType>(AmtVT)->getNumElements();
258 assert(AmtVT->isVectorTy() && AmtVT->getPrimitiveSizeInBits() == 128 &&
259 cast<VectorType>(AmtVT)->getElementType() == SVT &&
X86ISelLowering.cpp     [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRISelLowering.cpp 294 EVT AmtVT = Amt.getValueType();
295 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
296 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
301 EVT AmtVT = Amt.getValueType();
302 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
303 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 8732 EVT AmtVT = Amt.getValueType();
8734 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
8735 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
8739 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
8740 DAG.getConstant(-BitWidth, dl, AmtVT));
8761 EVT AmtVT = Amt.getValueType();
8763 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
8764 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
8768 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
8769 DAG.getConstant(-BitWidth, dl, AmtVT));
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 8129 EVT AmtVT = N1.getValueType();
8130 SDValue Bits = DAG.getConstant(Bitsize, dl, AmtVT);
8132 DAG.FoldConstantArithmetic(ISD::UREM, dl, AmtVT, {N1, Bits}))
12096 EVT AmtVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
12099 if (AmtVT != Amt.getValueType()) {
12100 Amt = DAG.getZExtOrTrunc(Amt, SL, AmtVT);

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