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    Searched refs:And0 (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonLoopIdiomRecognition.cpp 1632 Instruction *And0 = dyn_cast<Instruction>(I->getOperand(0));
1634 if (!And0 || !And1)
1636 if (And0->getOpcode() != Instruction::And ||
1639 if (And0->getOperand(1) != And1->getOperand(1))
1642 return B.CreateAnd(B.CreateXor(And0->getOperand(0), And1->getOperand(0)),
1643 And0->getOperand(1));
1764 Instruction *And0 = dyn_cast<Instruction>(Xor->getOperand(0));
1767 if (!And0 || And0->getOpcode() != Instruction::And)
1768 std::swap(And0, And1)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelDAGToDAG.cpp 2653 SDValue And0 = N->getOperand(0);
2655 if (And0.hasOneUse() && And1.hasOneUse() &&
2656 isOpcWithIntImmediate(And0.getNode(), ISD::AND, Mask0Imm) &&
2665 std::swap(And0, And1);
2670 SDValue Dst = And0->getOperand(0);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.cpp 874 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
879 if (And0.getOpcode() != ISD::AND)
882 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
915 And0.getOperand(0));
955 And0->getOperand(0));
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelDAGToDAG.cpp 4271 SDValue And0 = And->getOperand(0);
4289 if (!CurDAG->MaskedValueIsZero(And0, HighZeros))
4295 ReplaceNode(And, And0.getNode());
4302 SDValue NewAnd = CurDAG->getNode(ISD::AND, SDLoc(And), VT, And0, NewMask);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 6019 Register And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask).getReg(0);
6039 MIRBuilder.buildOr(Dst, And0, And1, Flags);

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