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    Searched refs:AndOpc (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIOptimizeExecMaskingPreRA.cpp 35 unsigned AndOpc;
134 if (!And || And->getOpcode() != AndOpc ||
270 if (I->getOpcode() == AndOpc && I->getOperand(0).getReg() == DstReg &&
315 AndOpc = Wave32 ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64;
SILowerControlFlow.cpp 78 unsigned AndOpc;
234 BuildMI(MBB, I, DL, TII->get(AndOpc), Tmp)
314 MachineInstr *And = BuildMI(MBB, ElsePt, DL, TII->get(AndOpc), DstReg)
377 And = BuildMI(MBB, &MI, DL, TII->get(AndOpc), AndReg)
783 AndOpc = AMDGPU::S_AND_B32;
793 AndOpc = AMDGPU::S_AND_B64;
SIWholeQuadMode.cpp 162 unsigned AndOpc;
970 NewTerm = BuildMI(MBB, MI, DL, TII->get(AndOpc), Exec)
979 NewTerm = BuildMI(MBB, &MI, DL, TII->get(AndOpc), Exec)
983 unsigned Opcode = KillVal ? AndN2Opc : AndOpc;
1150 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(AndOpc), Exec)
1523 AndOpc = AMDGPU::S_AND_B32;
1531 AndOpc = AMDGPU::S_AND_B64;
AMDGPUInstructionSelector.cpp 156 unsigned AndOpc =
158 BuildMI(*BB, &I, DL, TII.get(AndOpc), MaskedReg)
1908 unsigned AndOpc = IsVALU ? AMDGPU::V_AND_B32_e64 : AMDGPU::S_AND_B32;
1913 BuildMI(*MBB, I, DL, TII.get(AndOpc), TmpReg1)
SIInstrInfo.cpp 5140 unsigned AndOpc =
5194 BuildMI(LoopBB, I, DL, TII.get(AndOpc), AndReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstructionSelector.cpp 799 unsigned AndOpc;
801 AndOpc = X86::AND8ri;
803 AndOpc = X86::AND16ri8;
805 AndOpc = X86::AND32ri8;
807 AndOpc = X86::AND64ri8;
827 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AndOpc), DstReg)

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