| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86CallingConv.h | 24 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
28 ISD::ArgFlagsTy ArgFlags, CCState &State);
|
| X86CallingConv.cpp | 29 ISD::ArgFlagsTy &ArgFlags,
93 ISD::ArgFlagsTy &ArgFlags,
130 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
132 if (ArgFlags.isSecArgPass()) {
133 if (ArgFlags.isHva())
135 ArgFlags, State);
155 if (!ArgFlags.isHva() || ArgFlags.isHvaStart()) {
171 if (!ArgFlags.isHva()) {
180 return ArgFlags.isHva()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64CallingConvention.h | 20 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
24 ISD::ArgFlagsTy ArgFlags, CCState &State);
27 ISD::ArgFlagsTy ArgFlags, CCState &State);
30 ISD::ArgFlagsTy ArgFlags, CCState &State);
33 ISD::ArgFlagsTy ArgFlags, CCState &State);
36 ISD::ArgFlagsTy ArgFlags, CCState &State);
39 ISD::ArgFlagsTy ArgFlags, CCState &State);
41 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
44 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
48 ISD::ArgFlagsTy ArgFlags, CCState &State)
[all...] |
| AArch64CallingConvention.cpp | 43 MVT LocVT, ISD::ArgFlagsTy &ArgFlags,
53 ArgFlags.setInConsecutiveRegs(false);
54 ArgFlags.setInConsecutiveRegsLast(false);
72 ArgFlags, State))
76 ArgFlags.setInConsecutiveRegs(true);
77 ArgFlags.setInConsecutiveRegsLast(true);
106 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
114 if (!ArgFlags.isInConsecutiveRegsLast())
117 return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, Align(8));
125 ISD::ArgFlagsTy &ArgFlags, CCState &State)
[all...] |
| AArch64ISelLowering.cpp | 5538 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
5545 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
5564 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
5572 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMCallingConv.h | 21 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
24 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
27 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
30 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
33 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
37 ISD::ArgFlagsTy ArgFlags, CCState &State);
39 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
42 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
45 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
48 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
[all...] |
| ARMCallingConv.cpp | 51 ISD::ArgFlagsTy ArgFlags,
104 ISD::ArgFlagsTy ArgFlags,
136 ISD::ArgFlagsTy ArgFlags,
147 ISD::ArgFlagsTy ArgFlags,
149 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
172 ISD::ArgFlagsTy ArgFlags,
185 ValNo, ValVT, LocVT, LocInfo, ArgFlags.getNonZeroOrigAlign().value()));
187 if (!ArgFlags.isInConsecutiveRegsLast())
270 Alignment = ArgFlags.getNonZeroMemAlign() <= 4 ? Align(4) : Align(8);
301 ISD::ArgFlagsTy ArgFlags, CCState &State)
[all...] |
| ARMFastISel.cpp | 220 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1874 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1881 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
2221 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2225 ArgFlags.reserve(I->getNumOperands());
2240 ArgFlags.push_back(Flags);
2246 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2330 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2335 ArgFlags.reserve(arg_size);
2373 ArgFlags.push_back(Flags)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCCallingConv.h | 23 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
26 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
29 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
32 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
35 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
38 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
42 ISD::ArgFlagsTy ArgFlags, CCState &State);
|
| PPCCallingConv.cpp | 26 ISD::ArgFlagsTy &ArgFlags,
34 ISD::ArgFlagsTy &ArgFlags,
60 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
84 ISD::ArgFlagsTy &ArgFlags,
112 ISD::ArgFlagsTy &ArgFlags,
141 ISD::ArgFlagsTy &ArgFlags,
|
| PPCFastISel.cpp | 187 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1375 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1387 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS);
1603 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1608 ArgFlags.reserve(NumArgs);
1637 ArgFlags.push_back(Flags);
1644 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
|
| PPCISelLowering.cpp | 5689 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
5693 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
5697 ArgFlags, CCInfo);
6513 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
6525 if (ArgFlags.isNest())
6540 if (ArgFlags.isByVal()) {
6541 if (ArgFlags.getNonZeroByValAlign() > PtrAlign)
6545 const unsigned ByValSize = ArgFlags.getByValSize();
6585 LocInfo = ArgFlags.isSExt() ? CCValAssign::LocInfo::SExt
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 46 Align MinAlign, ISD::ArgFlagsTy ArgFlags) {
47 Align Alignment = ArgFlags.getNonZeroByValAlign();
48 unsigned Size = ArgFlags.getByValSize();
96 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
97 if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this))
109 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
110 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
123 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
124 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
136 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZCallingConv.h | 97 ISD::ArgFlagsTy &ArgFlags,
101 // ArgFlags.isSplit() is true on the first part of a i128 argument;
103 if (!ArgFlags.isSplit() && PendingMembers.empty())
111 if (!ArgFlags.isSplitEnd())
145 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
168 ISD::ArgFlagsTy &ArgFlags,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kCallingConv.h | 41 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
|
| /src/external/apache2/llvm/dist/clang/include/clang/Basic/ |
| IdentifierTable.h | 696 ArgFlags = 0x07
707 assert((InfoPtr & ArgFlags) == 0 &&"Insufficiently aligned IdentifierInfo");
714 assert((InfoPtr & ArgFlags) == 0 &&"Insufficiently aligned IdentifierInfo");
720 return reinterpret_cast<IdentifierInfo *>(InfoPtr & ~ArgFlags);
725 return reinterpret_cast<MultiKeywordSelector *>(InfoPtr & ~ArgFlags);
729 return InfoPtr & ArgFlags;
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 179 ISD::ArgFlagsTy ArgFlags, CCState &State);
186 ISD::ArgFlagsTy &ArgFlags, CCState &State);
450 ISD::ArgFlagsTy ArgFlags);
502 // Get a list of argflags for pending assignments.
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 499 ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
506 if (ArgFlags.isSExt())
508 else if (ArgFlags.isZExt())
515 if (ArgFlags.isByVal()) {
516 State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, Align(2), ArgFlags);
534 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
544 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 371 ISD::ArgFlagsTy ArgFlags, CCState &State) {
376 return CC_Lanai32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
382 if (ArgFlags.isSExt())
384 else if (ArgFlags.isZExt())
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 2851 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2865 if (ArgFlags.isByVal())
2869 if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
2872 if (ArgFlags.isSExt())
2874 else if (ArgFlags.isZExt())
2884 if (ArgFlags.isSExt())
2886 else if (ArgFlags.isZExt())
2899 Align OrigAlign = ArgFlags.getNonZeroOrigAlign();
2909 if (ArgFlags.isSplit()) {
2964 ISD::ArgFlagsTy ArgFlags, CCState &State)
[all...] |
| MipsFastISel.cpp | 274 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
279 ISD::ArgFlagsTy ArgFlags, CCState &State) {
285 ISD::ArgFlagsTy ArgFlags, CCState &State) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 43 ISD::ArgFlagsTy &ArgFlags, CCState &State)
45 assert (ArgFlags.isSRet());
56 ISD::ArgFlagsTy &ArgFlags, CCState &State)
82 ISD::ArgFlagsTy &ArgFlags, CCState &State)
106 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
151 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 6675 ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
6737 if (!IsFixed && ArgFlags.getNonZeroOrigAlign() == TwoXLenInBytes &&
6755 assert(!ArgFlags.isSplit() && PendingLocs.empty() &&
6783 if (!LocVT.isVector() && (ArgFlags.isSplit() || !PendingLocs.empty())) {
6788 PendingArgFlags.push_back(ArgFlags);
6789 if (!ArgFlags.isSplitEnd()) {
6796 if (!LocVT.isVector() && ArgFlags.isSplitEnd() && PendingLocs.size() <= 2) {
6805 ArgFlags);
6857 assert(ArgFlags.isSplitEnd() && "Expected ArgFlags.isSplitEnd()")
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 139 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
|
