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    Searched refs:ArgRC (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUCallLowering.cpp 783 const TargetRegisterClass *ArgRC;
786 std::tie(OutgoingArg, ArgRC, ArgTy) =
795 assert(IncomingArgRC == ArgRC);
800 LI->loadInputValue(InputReg, MIRBuilder, IncomingArg, ArgRC, ArgTy);
819 const TargetRegisterClass *ArgRC;
822 std::tie(OutgoingArg, ArgRC, ArgTy) =
825 std::tie(OutgoingArg, ArgRC, ArgTy) =
828 std::tie(OutgoingArg, ArgRC, ArgTy) =
AMDGPULegalizerInfo.h 95 const TargetRegisterClass *ArgRC, LLT ArgTy) const;
AMDGPULegalizerInfo.cpp 2722 const TargetRegisterClass *ArgRC,
2728 Register LiveIn = getFunctionLiveInPhysReg(B.getMF(), B.getTII(), SrcReg, *ArgRC,
2756 const TargetRegisterClass *ArgRC;
2758 std::tie(Arg, ArgRC, ArgTy) = MFI->getPreloadedValue(ArgType);
2762 return loadInputValue(DstReg, B, Arg, ArgRC, ArgTy);
SIISelLowering.cpp 2722 const TargetRegisterClass *ArgRC;
2725 std::tie(OutgoingArg, ArgRC, ArgTy) =
2735 assert(IncomingArgRC == ArgRC);
2738 EVT ArgVT = TRI->getSpillSize(*ArgRC) == 8 ? MVT::i64 : MVT::i32;
2742 InputReg = loadInputValue(DAG, ArgRC, ArgVT, DL, *IncomingArg);
2766 const TargetRegisterClass *ArgRC;
2769 std::tie(OutgoingArg, ArgRC, Ty) =
2772 std::tie(OutgoingArg, ArgRC, Ty) =
2775 std::tie(OutgoingArg, ArgRC, Ty) =
2792 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgX)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 16037 const TargetRegisterClass *ArgRC =
16040 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT))
16048 if (!TRI || TRI->getCommonSubClass(ArgRC, ResRC))

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