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  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenRegisters.h 82 // A subregister index is "artificial" if every subregister obtained
83 // from applying this index is artificial. Artificial subregister
85 bool Artificial;
157 bool Artificial;
340 /// A register class is artificial if all its members are artificial.
341 bool Artificial;
498 // A register unit is artificial if at least one of its roots is
499 // artificial
    [all...]
CodeGenRegisters.cpp 54 : TheDef(R), EnumValue(Enum), AllSuperRegsCovered(true), Artificial(true) {
66 Artificial(true) {}
162 Artificial = R->getValueAsBit("isArtificial");
276 if (!SR->Artificial)
277 Idx->Artificial = false;
388 SR->Artificial)
395 if (!I.Artificial)
757 Artificial = true;
762 Artificial &= Reg->Artificial;
    [all...]
RegisterInfoEmitter.cpp 220 if (Regs.empty() || RC.Artificial)
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MacroFusion.cpp 107 DAG.addEdge(SU, SDep(&SecondSU, SDep::Artificial));
119 DAG.addEdge(&FirstSU, SDep(SU, SDep::Artificial));
127 DAG.addEdge(&FirstSU, SDep(&SU, SDep::Artificial));
ScheduleDAG.cpp 99 case Artificial: dbgs() << " Artificial"; break;
ScheduleDAGInstrs.cpp 258 Dep = SDep(SU, SDep::Artificial);
885 SDep Dep(SU, SDep::Artificial);
MachineScheduler.cpp 1654 DAG->addEdge(Succ.getSUnit(), SDep(SUb, SDep::Artificial));
1668 DAG->addEdge(SUa, SDep(Pred.getSUnit(), SDep::Artificial));
MachinePipeliner.cpp 1240 // Do not process a boundary node, an artificial node.
1348 // Create artificial dependencies between the source of COPY/REG_SEQUENCE that
1350 // additional copies that are needed across iterations. An artificial dependence
1358 // USEOfPHI -------Artificial-Dep---> SRCOfCopy
1416 // Add the artificial dependencies if it does not form a cycle.
1420 Src->addPred(SDep(I, SDep::Artificial));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUExportClustering.cpp 72 DAG->addEdge(ChainHead, SDep(PredSU, SDep::Artificial));
AMDGPUSubtarget.cpp 911 if (SU->addPred(SDep(From, SDep::Artificial), false))
917 SUv->addPred(SDep(SU, SDep::Artificial), false);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ScheduleDAG.h 59 // Strong dependencies must be respected by the scheduler. Artificial
72 Artificial, ///< Arbitrary strong DAG edge (no real dependence).
199 /// "artificial", meaning it isn't necessary for correctness.
201 return getKind() == Order && Contents.OrdKind == Artificial;
205 /// meaning it is artificial and wants to be adjacent.
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGRRList.cpp 575 // CALLSEQ_BEGIN. Inject an artificial physical register dependence between
1193 AddPredQueued(NewSU, SDep(SU, SDep::Artificial));
1251 AddPredQueued(SuccSU, SDep(CopyFromSU, SDep::Artificial));
1524 LLVM_DEBUG(dbgs() << "ARTIFICIAL edge from SU(" << BtSU->NodeNum
1526 AddPredQueued(TrySU, SDep(BtSU, SDep::Artificial));
1580 AddPredQueued(TrySU, SDep(Copies.front(), SDep::Artificial));
1587 AddPredQueued(NewDef, SDep(TrySU, SDep::Artificial));
3123 scheduleDAG->AddPredQueued(&SU, SDep(SuccSU, SDep::Artificial));
ScheduleDAGFast.cpp 597 AddPred(TrySU, SDep(Copies.front(), SDep::Artificial));
604 AddPred(NewDef, SDep(TrySU, SDep::Artificial));
  /src/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.arch/
arc-decode-insn.S 397 ; Artificial nop, so that first b will not branch to itself.
  /src/external/gpl3/gdb/dist/gdb/testsuite/gdb.arch/
arc-decode-insn.S 397 ; Artificial nop, so that first b will not branch to itself.
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonSubtarget.cpp 338 // Create artificial edges between loads that could likely cause a bank
370 // Bits 3 and 4 are the same, add an artificial edge and set extra
372 SDep A(&S0, SDep::Artificial);
  /src/external/apache2/llvm/dist/llvm/bindings/ocaml/debuginfo/
llvm_debuginfo.ml 70 | Artificial
llvm_debuginfo.mli 70 | Artificial

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