| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 54 /// AssertSext, AssertZext - These nodes record if a register contains a
59 AssertSext,
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| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 107 case ISD::AssertSext: return "AssertSext";
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| LegalizeIntegerTypes.cpp | 56 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
249 return DAG.getNode(ISD::AssertSext, SDLoc(N),
623 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
2071 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
2855 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
2859 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
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| LegalizeVectorOps.cpp | 711 NewOpc = ISD::AssertSext;
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| SelectionDAGBuilder.cpp | 163 /// (ISD::AssertSext).
325 /// ValueVT (ISD::AssertSext).
865 // now, just use the tightest assertzext/assertsext possible.
880 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
5478 case ISD::AssertSext:
9713 AssertOp = ISD::AssertSext;
10264 AssertOp = ISD::AssertSext;
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| SelectionDAGISel.cpp | 2857 case ISD::AssertSext:
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| DAGCombiner.cpp | 1224 case ISD::AssertSext:
1226 return DAG.getNode(ISD::AssertSext, DL, PVT, Op0, Op.getOperand(1));
1672 case ISD::AssertSext:
2629 // add N0, (and (AssertSext X, i1), 1) --> sub N0, X
2630 // sub N0, (and (AssertSext X, i1), 1) --> add N0, X
11534 // If we have (AssertZext (truncate (AssertSext X, iX)), iY) and Y is smaller
11536 // AssertSExt.
11538 N0.getOperand(0).getOpcode() == ISD::AssertSext &&
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| LegalizeDAG.cpp | 2788 LHS = DAG.getNode(ISD::AssertSext, dl, OuterType, Res,
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| SelectionDAG.cpp | 3697 case ISD::AssertSext:
5661 case ISD::AssertSext:
5668 "AssertSExt/AssertZExt type should be the vector element type "
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 453 // up to 64 bits. AssertSext/AssertZext aren't saying anything about the upper
459 Opc != ISD::CopyFromReg && Opc != ISD::AssertSext &&
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| AArch64ISelLowering.cpp | 12069 case ISD::AssertSext:
12131 ExtendOpcode == ISD::AssertSext;
14970 case ISD::AssertSext: {
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| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 340 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 452 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
611 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
1329 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.cpp | 471 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
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| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelDAGToDAG.cpp | 1258 if (N.getOpcode() == ISD::AssertSext &&
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEISelLowering.cpp | 429 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
777 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelLowering.cpp | 1177 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 661 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 564 setTargetDAGCombine(ISD::AssertSext);
4088 case ISD::AssertSext:
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| SIISelLowering.cpp | 1656 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext;
2452 Val = DAG.getNode(ISD::AssertSext, DL, VT, Val,
2662 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 3533 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
3584 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 1528 case ISD::AssertSext:
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| HexagonISelLowering.cpp | 1061 if (Op.getOpcode() != ISD::AssertSext)
1066 // The type that was sign-extended to get the AssertSext must be
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| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.cpp | 907 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
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| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 4197 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
5128 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
6773 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue,
16487 ExtsSrc.getOperand(0).getOpcode() == ISD::AssertSext)
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