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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 54 /// AssertSext, AssertZext - These nodes record if a register contains a
60 AssertZext,
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelDAGToDAG.cpp 1263 if (N.getOpcode() == ISD::AssertZext &&
1281 if (N.getOpcode() == ISD::AssertZext &&
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGDumper.cpp 108 case ISD::AssertZext: return "AssertZext";
LegalizeIntegerTypes.cpp 57 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
256 return DAG.getNode(ISD::AssertZext, SDLoc(N),
623 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
2072 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
2877 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
2881 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
LegalizeVectorOps.cpp 709 NewOpc = ISD::AssertZext;
SelectionDAGBuilder.cpp 162 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
324 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
865 // now, just use the tightest assertzext/assertsext possible.
880 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
5477 case ISD::AssertZext:
8957 SDValue ZExt = DAG.getNode(ISD::AssertZext, SL, Op.getValueType(), Op,
9715 AssertOp = ISD::AssertZext;
10266 AssertOp = ISD::AssertZext;
10306 if (Res.getOpcode() == ISD::AssertZext)
LegalizeDAG.cpp 764 Result = DAG.getNode(ISD::AssertZext, dl,
2795 LHS = DAG.getNode(ISD::AssertZext, dl, OuterType, Res,
SelectionDAGISel.cpp 2858 case ISD::AssertZext:
DAGCombiner.cpp 1228 case ISD::AssertZext:
1230 return DAG.getNode(ISD::AssertZext, DL, PVT, Op0, Op.getOperand(1));
1673 case ISD::AssertZext: return visitAssertExt(N);
5359 case ISD::AssertZext: {
5362 EVT VT = Op.getOpcode() == ISD::AssertZext ?
11534 // If we have (AssertZext (truncate (AssertSext X, iX)), iY) and Y is smaller
11535 // than X. Just move the AssertZext in front of the truncate and drop the
11539 Opcode == ISD::AssertZext) {
SelectionDAG.cpp 3299 case ISD::AssertZext: {
3700 case ISD::AssertZext:
5662 case ISD::AssertZext: {
5668 "AssertSExt/AssertZExt type should be the vector element type "
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.h 453 // up to 64 bits. AssertSext/AssertZext aren't saying anything about the upper
460 Opc != ISD::AssertZext;
AArch64ISelLowering.cpp 5022 ArgValue = DAG.getNode(ISD::AssertZext, DL, ArgValue.getValueType(),
7520 FrameAddr = DAG.getNode(ISD::AssertZext, DL, MVT::i64, FrameAddr,
12070 case ISD::AssertZext:
12133 ExtendOpcode != ISD::AssertZext && ExtendOpcode != ISD::AND)
14979 case ISD::AssertZext: {
  /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
BPFISelLowering.cpp 343 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
  /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
LanaiISelLowering.cpp 474 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 1656 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext;
2407 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
2438 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val,
2457 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val,
2657 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
5756 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param,
9052 SDValue Ext = DAG.getNode(ISD::AssertZext, SL, VT, BFE,
11120 if (Op.getOpcode() == ISD::AssertZext)
AMDGPUISelLowering.cpp 563 setTargetDAGCombine(ISD::AssertZext);
2982 // (vt2 (assertzext (truncate vt0:x), vt1)) ->
2983 // (vt2 (truncate (assertzext vt0:x, vt1)))
4087 case ISD::AssertZext:
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
M68kISelLowering.cpp 259 if (TruncInput.getOpcode() == ISD::AssertZext &&
910 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/
VEISelLowering.cpp 433 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
781 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.cpp 504 setTargetDAGCombine(ISD::AssertZext);
3527 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
3589 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRISelLowering.cpp 1182 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430ISelLowering.cpp 664 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelLowering.cpp 615 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
1333 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelDAGToDAG.cpp 1529 case ISD::AssertZext:
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelDAGToDAG.cpp 1626 case ISD::AssertZext: {
1627 // For AssertZext, we look through the operand and
1638 // These bits are known to be zero but the AssertZext may be from a value
3019 (Input.getOperand(0).getOpcode() == ISD::AssertZext ||
PPCISelLowering.cpp 4200 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
5123 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
6776 ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue,

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