HomeSort by: relevance | last modified time | path
    Searched refs:AssignedReg (Results 1 - 7 of 7) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
InlineAsmLowering.cpp 99 Register AssignedReg;
101 std::tie(AssignedReg, RC) = TLI.getRegForInlineAsmConstraint(
127 if (AssignedReg) {
128 for (; *I != AssignedReg; ++I)
129 assert(I != RC->end() && "AssignedReg should be a member of provided RC");
132 // Finally, assign the registers. If the AssignedReg isn't set, create virtual
136 Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RC);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCFastISel.cpp 607 unsigned AssignedReg = FuncInfo.ValueMap[I];
609 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
1172 unsigned AssignedReg = FuncInfo.ValueMap[I];
1174 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
1278 unsigned AssignedReg = FuncInfo.ValueMap[I];
1280 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1923 unsigned AssignedReg = FuncInfo.ValueMap[I]
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
RegAllocFast.cpp 276 MCPhysReg AssignedReg, bool Kill, bool LiveOut);
402 /// Insert spill instruction for \p AssignedReg before \p Before. Update
405 MCPhysReg AssignedReg, bool Kill, bool LiveOut) {
407 << " in " << printReg(AssignedReg, TRI));
412 TII->storeRegToStackSlot(*MBB, Before, AssignedReg, Kill, FI, &RC, TRI);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUTargetTransformInfo.cpp 935 Register AssignedReg;
937 std::tie(AssignedReg, RC) = TLI->getRegForInlineAsmConstraint(
939 if (AssignedReg) {
942 RC = TRI->getPhysRegClass(AssignedReg);
SIISelLowering.cpp 12261 unsigned AssignedReg;
12263 std::tie(AssignedReg, RC) = getRegForInlineAsmConstraint(
12267 if (AssignedReg != 0 && SIRI->isSGPRReg(MRI, AssignedReg))
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
FastISel.cpp 371 Register &AssignedReg = FuncInfo.ValueMap[I];
372 if (!AssignedReg)
374 AssignedReg = Reg;
375 else if (Reg != AssignedReg) {
376 // Arrange for uses of AssignedReg to be replaced by uses of Reg.
378 FuncInfo.RegFixups[AssignedReg + i] = Reg + i;
382 AssignedReg = Reg;
SelectionDAGBuilder.cpp 8221 unsigned AssignedReg;
8223 std::tie(AssignedReg, RC) = TLI.getRegForInlineAsmConstraint(
8294 if (AssignedReg) {
8295 for (; *I != AssignedReg; ++I)
8296 assert(I != RC->end() && "AssignedReg should be member of RC");
8301 Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RC);

Completed in 74 milliseconds