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    Searched refs:BB1 (Results 1 - 20 of 20) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
PostDominators.cpp 58 const BasicBlock *BB1 = I1->getParent();
61 if (BB1 != BB2)
62 return Base::dominates(BB1, BB2);
69 BasicBlock::const_iterator I = BB1->begin();
  /src/external/apache2/llvm/dist/llvm/include/llvm/Transforms/Utils/
CodeMoverUtils.h 32 /// Return true if \p BB0 and \p BB1 are control flow equivalent.
35 bool isControlFlowEquivalent(const BasicBlock &BB0, const BasicBlock &BB1,
SampleProfileLoaderBaseImpl.h 129 void findEquivalencesFor(BasicBlockT *BB1,
164 /// Two blocks BB1 and BB2 are in the same equivalence class if they
382 /// number of times as \p BB1. To do this, it traverses all the
383 /// descendants of \p BB1 in the dominator or post-dominator tree.
385 /// A block BB2 will be in the same equivalence class as \p BB1 if
388 /// 1- \p BB1 is a descendant of BB2 in the opposite tree. So, if BB2
389 /// is a descendant of \p BB1 in the dominator tree, then BB2 should
390 /// dominate BB1 in the post-dominator tree.
392 /// 2- Both BB2 and \p BB1 must be in the same loop.
395 /// equivalence class to \p BB1
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsMCInstLower.h 43 MCOperand createSub(MachineBasicBlock *BB1, MachineBasicBlock *BB2,
MipsMCInstLower.cpp 204 MCOperand MipsMCInstLower::createSub(MachineBasicBlock *BB1,
207 const MCSymbolRefExpr *Sym1 = MCSymbolRefExpr::create(BB1->getSymbol(), *Ctx);
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
CodeMoverUtils.cpp 39 /// example, `br %cond, bb0, bb1` %cond is a control condition of bb0 with the
40 /// integer field equals to true, while %cond is a control condition of bb1 with
235 bool llvm::isControlFlowEquivalent(const BasicBlock &BB0, const BasicBlock &BB1,
238 if (&BB0 == &BB1)
241 if ((DT.dominates(&BB0, &BB1) && PDT.dominates(&BB1, &BB0)) ||
242 (PDT.dominates(&BB0, &BB1) && DT.dominates(&BB1, &BB0)))
245 // If the set of conditions required to execute BB0 and BB1 from their common
246 // dominator are the same, then BB0 and BB1 are control flow equivalent
    [all...]
IntegerDivision.cpp 192 // | | bb1 |
227 BasicBlock *BB1 = BasicBlock::Create(Builder.getContext(),
228 "udiv-bb1", F, End);
249 // ; br i1 %earlyRet, label %end, label %bb1
262 Builder.CreateCondBr(EarlyRet, End, BB1);
264 // ; bb1: ; preds = %special-cases
270 Builder.SetInsertPoint(BB1);
277 // ; preheader: ; preds = %bb1
323 // ; loop-exit: ; preds = %do-while, %bb1
324 // ; %carry_2 = phi i32 [ 0, %bb1 ], [ %carry, %do-while
    [all...]
SimplifyCFG.cpp 1379 static bool isSafeToHoistInvoke(BasicBlock *BB1, BasicBlock *BB2,
1381 for (BasicBlock *Succ : successors(BB1)) {
1383 Value *BB1V = PN.getIncomingValueForBlock(BB1);
1395 /// Given a conditional branch that goes to BB1 and BB2, hoist any common code
1397 /// guarantees that BI's block dominates BB1 and BB2. If EqTermsOnly is given,
1405 // O(M*N) situations here where M and N are the sizes of BB1 and BB2. As
1408 BasicBlock *BB1 = BI->getSuccessor(0); // The true destination.
1411 BasicBlock::iterator BB1_Itr = BB1->begin();
1426 (isa<InvokeInst>(I1) && !isSafeToHoistInvoke(BB1, BB2, I1, I2)) ||
1487 BB1->getInstList(), I1)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
MergedLoadStoreMotion.cpp 187 StoreInst *MergedLoadStoreMotion::canSinkFromBlock(BasicBlock *BB1,
191 for (Instruction &Inst : reverse(*BB1)) {
199 !isStoreSinkBarrierInRange(*Store1->getNextNode(), BB1->back(), Loc1) &&
ConstantHoisting.cpp 343 BasicBlock *BB, *BB1, *BB2;
344 BB1 = BBs.pop_back_val();
346 BB = DT->findNearestCommonDominator(BB1, BB2);
LoopInterchange.cpp 1412 /// Swap instructions between \p BB1 and \p BB2 but keep terminators intact.
1413 static void swapBBContents(BasicBlock *BB1, BasicBlock *BB2) {
1414 // Save all non-terminator instructions of BB1 into TempInstrs and unlink them
1415 // from BB1 afterwards.
1416 auto Iter = map_range(*BB1, [](Instruction &I) { return &I; });
1421 // Move instructions from BB2 to BB1.
1422 moveBBContents(BB2, BB1->getTerminator());
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Instrumentation/
CFGMST.h 61 // Union BB1 and BB2 into the same group and return true.
62 // Returns false if BB1 and BB2 are already in the same group.
63 bool unionGroups(const BasicBlock *BB1, const BasicBlock *BB2) {
64 BBInfo *BB1G = findAndCompressGroup(&getBBInfo(BB1));
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ModuloSchedule.h 195 void generateExistingPhis(MachineBasicBlock *NewBB, MachineBasicBlock *BB1,
200 void generatePhis(MachineBasicBlock *NewBB, MachineBasicBlock *BB1,
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineCSE.cpp 836 auto BB = MBB->getBasicBlock(), BB1 = MBB1->getBasicBlock();
837 if (BB != nullptr && BB1 != nullptr &&
838 (isPotentiallyReachable(BB1, BB) ||
839 isPotentiallyReachable(BB, BB1))) {
ModuloSchedule.cpp 365 MachineBasicBlock *NewBB, MachineBasicBlock *BB1, MachineBasicBlock *BB2,
553 NewPhi.addReg(PhiOp1).addMBB(BB1);
603 MachineBasicBlock *NewBB, MachineBasicBlock *BB1, MachineBasicBlock *BB2,
669 NewPhi.addReg(PhiOp1).addMBB(BB1);
  /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/
LoopInfoImpl.h 632 bool compareVectors(std::vector<T> &BB1, std::vector<T> &BB2) {
633 llvm::sort(BB1);
635 return BB1 == BB2;
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCMIPeephole.cpp 1105 // If BB1 and BB2 are non-NULL, we also track PHI instruction in BB2
1106 // assuming that the control comes from BB1 into BB2.
1107 static unsigned getSrcVReg(unsigned Reg, MachineBasicBlock *BB1,
1113 if (BB1 && Inst->getOpcode() == PPC::PHI && Inst->getParent() == BB2) {
1114 NextReg = getIncomingRegForBlock(Inst, BB1);
1116 BB1 = nullptr;
  /src/external/apache2/llvm/dist/clang/lib/Analysis/
ThreadSafetyCommon.cpp 915 til::BasicBlock *BB1 = *It ? lookupBlock(*It) : nullptr;
919 auto *Tm = new (Arena) til::Branch(C, BB1, BB2);
  /src/external/gpl3/gcc/dist/libgcc/config/avr/
lib1funcs.S 1264 #define BB1 BB0+1
1329 #undef BB1
  /src/external/gpl3/gcc.old/dist/libgcc/config/avr/
lib1funcs.S 1259 #define BB1 BB0+1
1324 #undef BB1

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