| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 2361 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll
2386 { ISD::BITREVERSE, MVT::v8i64, 5 },
2387 { ISD::BITREVERSE, MVT::v16i32, 5 },
2388 { ISD::BITREVERSE, MVT::v32i16, 5 },
2389 { ISD::BITREVERSE, MVT::v64i8, 5 },
2426 { ISD::BITREVERSE, MVT::v8i64, 36 },
2427 { ISD::BITREVERSE, MVT::v16i32, 24 },
2428 { ISD::BITREVERSE, MVT::v32i16, 10 },
2429 { ISD::BITREVERSE, MVT::v64i8, 10 }
[all...] |
| X86ISelLowering.cpp | 1106 setOperationAction(ISD::BITREVERSE, MVT::v16i8, Custom);
1197 // XOP can efficiently perform BITREVERSE with VPPERM.
1199 setOperationAction(ISD::BITREVERSE, VT, Custom);
1203 setOperationAction(ISD::BITREVERSE, VT, Custom);
1308 setOperationAction(ISD::BITREVERSE, MVT::v32i8, Custom);
1650 setOperationAction(ISD::BITREVERSE, MVT::v64i8, Custom);
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 660 BITREVERSE,
|
| BasicTTIImpl.h | 1841 case Intrinsic::bitreverse:
1842 ISDs.push_back(ISD::BITREVERSE);
|
| /src/external/gpl3/gcc/dist/gcc/ |
| rtl.def | 668 DEF_RTL_EXPR(BITREVERSE, "bitreverse", "e", RTX_UNARY)
|
| simplify-rtx.cc | 1051 if (GET_CODE (op) == BSWAP || GET_CODE (op) == BITREVERSE)
1430 case BITREVERSE:
1460 case BITREVERSE:
1494 case BITREVERSE:
1495 /* (bitreverse (bitreverse x)) -> x. */
1496 if (GET_CODE (op) == BITREVERSE)
2133 case BITREVERSE:
2134 result = wi::bitreverse (op0);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 391 case ISD::BITREVERSE:
781 case ISD::BITREVERSE:
1121 if (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, VT.getScalarType())) {
1128 // to BSWAP shuffle the bytes and then perform the BITREVERSE on the byte
1137 (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, ByteVT) ||
1146 Op = DAG.getNode(ISD::BITREVERSE, DL, ByteVT, Op);
|
| SelectionDAGDumper.cpp | 422 case ISD::BITREVERSE: return "bitreverse";
|
| LegalizeIntegerTypes.cpp | 59 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
438 // Helper for BSWAP/BITREVERSE promotion to ensure we can fit any shift amount
484 // If the larger BITREVERSE isn't supported by the target, try to expand now.
489 !TLI.isOperationLegalOrCustom(ISD::BITREVERSE, NVT)) {
497 DAG.getNode(ISD::BITREVERSE, dl, NVT, Op),
2073 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
2891 Lo = DAG.getNode(ISD::BITREVERSE, dl, Lo.getValueType(), Lo);
2892 Hi = DAG.getNode(ISD::BITREVERSE, dl, Hi.getValueType(), Hi);
|
| LegalizeVectorTypes.cpp | 74 case ISD::BITREVERSE:
967 case ISD::BITREVERSE:
3140 case ISD::BITREVERSE:
|
| LegalizeDAG.cpp | 2691 case ISD::BITREVERSE:
4427 case ISD::BITREVERSE:
|
| SelectionDAG.cpp | 3459 case ISD::BITREVERSE: {
4640 case ISD::BITREVERSE:
4767 case ISD::BITREVERSE:
4955 case ISD::BITREVERSE:
4957 "Invalid BITREVERSE!");
|
| DAGCombiner.cpp | 1658 case ISD::BITREVERSE: return visitBITREVERSE(N);
9087 // fold (bitreverse c1) -> c2
9089 return DAG.getNode(ISD::BITREVERSE, SDLoc(N), VT, N0);
9090 // fold (bitreverse (bitreverse x)) -> x
9091 if (N0.getOpcode() == ISD::BITREVERSE)
|
| SelectionDAGBuilder.cpp | 6368 case Intrinsic::bitreverse:
6369 setValue(&I, DAG.getNode(ISD::BITREVERSE, sdl,
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 798 setOperationAction(ISD::BITREVERSE, VT, Expand);
|
| CodeGenPrepare.cpp | 7920 /// Given an OR instruction, check to see if this is a bitreverse
7924 !TLI->isOperationLegalOrCustom(ISD::BITREVERSE,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 109 setOperationAction(ISD::BITREVERSE , MVT::i32, Legal);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 1573 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
1574 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 402 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
403 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 379 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
380 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
1026 setOperationAction(ISD::BITREVERSE, MVT::v8i8, Legal);
1027 setOperationAction(ISD::BITREVERSE, MVT::v16i8, Legal);
1124 setOperationAction(ISD::BITREVERSE, VT, Custom);
1285 setOperationAction(ISD::BITREVERSE, MVT::v1i64, Custom);
1327 setOperationAction(ISD::BITREVERSE, VT, Custom);
1463 setOperationAction(ISD::BITREVERSE, VT, Custom);
4701 case ISD::BITREVERSE:
6872 SDValue RBIT = DAG.getNode(ISD::BITREVERSE, DL, VT, Op.getOperand(0))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 251 // Custom lower bswap/bitreverse so we can convert them to GREVI to enable
253 setOperationAction(ISD::BITREVERSE, XLenVT, Custom);
257 setOperationAction(ISD::BITREVERSE, MVT::i32, Custom);
1992 case ISD::BITREVERSE: {
1993 // Convert BSWAP/BITREVERSE to GREVI to enable GREVI combinining.
1999 // If this is BSWAP rather than BITREVERSE, clear the lower 3 bits.
4879 case ISD::BITREVERSE: {
4884 unsigned Imm = N->getOpcode() == ISD::BITREVERSE ? 31 : 24;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEISelLowering.cpp | 187 // VE has only 64 bits instructions which work as i64 BITREVERSE/CTLZ/CTPOP
190 setOperationAction(ISD::BITREVERSE, IntVT, Act);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 278 setOperationAction(ISD::BITREVERSE, VT, Legal);
1150 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
6212 SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, VT, N->getOperand(0));
8165 SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, MVT::i32, cast);
9516 DAG.getNode(ISD::BITREVERSE, dl, MVT::i32, Load),
9573 DAG.getNode(ISD::BITREVERSE, dl, MVT::i32, GRP),
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 391 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
392 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
513 setOperationAction(ISD::BITREVERSE, MVT::i16, Promote);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 162 // Match BITREVERSE to customized fast code sequence in the td file.
163 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
164 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
|
