| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_gem_gtt.h | 38 #define PIN_NOEVICT BIT_ULL(0)
39 #define PIN_NOSEARCH BIT_ULL(1)
40 #define PIN_NONBLOCK BIT_ULL(2)
41 #define PIN_MAPPABLE BIT_ULL(3)
42 #define PIN_ZONE_4G BIT_ULL(4)
43 #define PIN_HIGH BIT_ULL(5)
44 #define PIN_OFFSET_BIAS BIT_ULL(6)
45 #define PIN_OFFSET_FIXED BIT_ULL(7)
47 #define PIN_UPDATE BIT_ULL(9)
48 #define PIN_GLOBAL BIT_ULL(10) /* I915_VMA_GLOBAL_BIND *
[all...] |
| i915_pmu.c | 74 return BIT_ULL(config_enabled_bit(config));
660 config_enabled_mask(I915_PMU_RC6_RESIDENCY) & BIT_ULL(bit)) {
666 pmu->enable |= BIT_ULL(bit);
747 pmu->enable &= ~BIT_ULL(bit);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_display_power.c | 222 for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain)) {
1873 power_domains->async_put_domains[0] &= ~BIT_ULL(domain);
1874 power_domains->async_put_domains[1] &= ~BIT_ULL(domain);
1884 if (!(async_put_domains_mask(power_domains) & BIT_ULL(domain)))
1913 for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
2000 WARN(async_put_domains_mask(power_domains) & BIT_ULL(domain),
2006 for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain))
2151 power_domains->async_put_domains[1] |= BIT_ULL(domain);
2153 power_domains->async_put_domains[0] |= BIT_ULL(domain);
2246 BIT_ULL(POWER_DOMAIN_PIPE_A) |
[all...] |
| intel_display_power.h | 226 for_each_if(BIT_ULL(domain) & (mask))
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/mmu/ |
| nouveau_nvkm_subdev_mmu_vmmgv100.c | 46 mask = BIT_ULL(0);
51 if (mask & BIT_ULL(i)) {
|
| nouveau_nvkm_subdev_mmu_vmmgp100.c | 74 if ((data & BIT_ULL(0)) && (data & (3ULL << 1)) != 0) {
75 VMM_WO064(pt, vmm, ptei * 8, data & ~BIT_ULL(0));
95 data |= BIT_ULL(6); /* RO. */
108 data |= BIT_ULL(3); /* VOL. */
109 data |= BIT_ULL(0); /* VALID. */
114 data |= BIT_ULL(0); /* VALID. */
177 VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(3) /* VOL. */, ptes);
199 VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(5) /* PRIV. */, ptes);
237 *data |= BIT_ULL(3); /* VOL. */
270 VMM_FO128(pt, vmm, pdei * 0x10, BIT_ULL(3) /* VOL_BIG. */, 0ULL, pdes)
[all...] |
| nouveau_nvkm_subdev_mmu_vmmgm200.c | 37 VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(32) /* VOL. */, ptes);
64 VMM_FO064(pt, vmm, pdei * 8, BIT_ULL(35) /* VOL_BIG. */, pdes);
106 base |= BIT_ULL(11);
|
| nouveau_nvkm_subdev_mmu_vmmgk104.c | 34 VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(1) /* PRIV. */, ptes);
|
| nouveau_nvkm_subdev_mmu_vmmgf100.c | 49 data |= BIT_ULL(60);
128 data |= BIT_ULL(35); /* VOL */
142 data |= BIT_ULL(34); /* VOL */
359 base |= BIT_ULL(2) /* VOL. */;
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvif/ |
| nouveau_nvif_fifo.c | 66 if (a->v.runlists.data & BIT_ULL(i))
99 runm |= BIT_ULL(i);
|
| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_color_mgmt.c | 137 u64 mag = (user_input & ~BIT_ULL(63)) >> (32 - n);
138 bool negative = !!(user_input & BIT_ULL(63));
144 BIT_ULL(n + m - 1) : BIT_ULL(n + m - 1) - 1);
|
| drm_client_modeset.c | 381 const u64 mask = BIT_ULL(connector_count) - 1;
398 if (conn_configured & BIT_ULL(i))
402 conn_configured |= BIT_ULL(i);
467 conn_configured |= BIT_ULL(i);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/selftests/ |
| i915_syncmap.c | 302 u64 context = BIT_ULL(order);
351 u64 context = step * BIT_ULL(order);
368 u64 context = step * BIT_ULL(order);
390 u64 context = step * BIT_ULL(order);
474 u64 context = idx * BIT_ULL(order) + idx;
|
| i915_gem_gtt.c | 255 GEM_BUG_ON(count * BIT_ULL(size) > vm->total);
256 GEM_BUG_ON(hole_start + count * BIT_ULL(size) > hole_end);
264 obj = fake_dma_object(vm->i915, BIT_ULL(size));
270 GEM_BUG_ON(obj->base.size != BIT_ULL(size));
279 u64 addr = hole_start + order[n] * BIT_ULL(size);
282 GEM_BUG_ON(addr + BIT_ULL(size) > vm->total);
292 vm->allocate_va_range(vm, addr, BIT_ULL(size)))
296 mock_vma->node.size = BIT_ULL(size);
307 u64 addr = hole_start + order[n] * BIT_ULL(size);
310 GEM_BUG_ON(addr + BIT_ULL(size) > vm->total)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/fifo/ |
| nouveau_nvkm_engine_fifo_gpfifogk104.c | 261 *runlists = BIT_ULL(runlist);
266 subdevs |= BIT_ULL(fifo->engine[i].engine->subdev.index);
269 if (subdevs & BIT_ULL(NVKM_ENGINE_GR))
270 subdevs |= BIT_ULL(NVKM_ENGINE_SW);
|
| nouveau_nvkm_engine_fifo_gpfifogv100.c | 144 *runlists = BIT_ULL(runlist);
149 subdevs |= BIT_ULL(fifo->engine[i].engine->subdev.index);
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/top/ |
| nouveau_nvkm_subdev_top_base.c | 108 subdevs |= BIT_ULL(info->index);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gt/ |
| intel_gtt.h | 58 #define I915_GTT_PAGE_SIZE_4K BIT_ULL(12)
59 #define I915_GTT_PAGE_SIZE_64K BIT_ULL(16)
60 #define I915_GTT_PAGE_SIZE_2M BIT_ULL(21)
|
| gen8_ppgtt.c | 244 GEM_BUG_ON(!IS_ALIGNED(start, BIT_ULL(GEN8_PTE_SHIFT)));
245 GEM_BUG_ON(!IS_ALIGNED(length, BIT_ULL(GEN8_PTE_SHIFT)));
365 GEM_BUG_ON(!IS_ALIGNED(start, BIT_ULL(GEN8_PTE_SHIFT)));
366 GEM_BUG_ON(!IS_ALIGNED(length, BIT_ULL(GEN8_PTE_SHIFT)));
|
| intel_ppgtt.c | 224 ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
|
| intel_rc6.c | 733 overflow_hw = BIT_ULL(40);
745 overflow_hw = BIT_ULL(32);
|
| intel_timeline.c | 95 hwsp->free_bitmap &= ~BIT_ULL(*cacheline);
117 hwsp->free_bitmap |= BIT_ULL(cacheline);
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv50/ |
| nouveau_dispnv50_base907c.c | 99 bool sign = in & BIT_ULL(63);
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/mc/ |
| nouveau_nvkm_subdev_mc_base.c | 101 subdevs &= ~BIT_ULL(subidx);
|
| /src/sys/external/bsd/common/include/linux/ |
| bitops.h | 117 #define BIT_ULL(n) ((unsigned long long)__BIT(n))
|
