| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64SLSHardening.cpp | 111 case AArch64::BLR:
166 // register to not be used in BLR. See comment in ConvertBLRToBL for more
204 // based on which registers are actually used in BLR instructions in this
247 // Transform a BLR to a BL as follows:
252 // | BLR xN |
273 // This function merely needs to transform BLR xN into BL
277 // above mitigation only works if the original BLR instruction was not
278 // BLR X16 nor BLR X17. Code generation before must make sure that no BLR
[all...] |
| AArch64AsmPrinter.cpp | 293 // BLR X16 ; call the tracing trampoline
1002 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg));
1038 CallOpcode = AArch64::BLR;
1286 /// blr x1
1337 MCInst Blr;
1338 Blr.setOpcode(AArch64::BLR);
1339 Blr.addOperand(MCOperand::createReg(AArch64::X1));
1340 EmitToStreamer(*OutStreamer, Blr);
|
| AArch64ExpandPseudoInsts.cpp | 670 unsigned Opc = CallTarget.isGlobal() ? AArch64::BL : AArch64::BLR;
|
| AArch64InstrInfo.cpp | 6662 ((LastInstrOpcode == AArch64::BLR ||
7035 if (MI.getOpcode() == AArch64::BLR ||
7184 assert(Call->getOpcode() == AArch64::BLR ||
7544 return AArch64::BLR;
|
| /src/sys/external/bsd/compiler_rt/dist/lib/xray/ |
| xray_trampoline_AArch64.S | 40 BLR X2
84 BLR X2
130 BLR X2
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCEarlyReturn.cpp | 42 // branch-to-blr sequences.
58 // The block must be essentially empty except for the blr.
60 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) ||
79 // branch with a blr.
157 // We now might be able to merge this blr-only block into its
162 // Move the blr into the preceding block.
|
| PPCInstrInfo.cpp | 93 STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
2163 if (OpC == PPC::BLR || OpC == PPC::BLR8) {
|
| PPCFrameLowering.cpp | 1877 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
|
| /src/external/gpl3/gdb.old/dist/gdb/arch/ |
| aarch64-insn.h | 70 /* BLR 1101 0110 0011 1111 0000 00rr rrr0 0000 */
72 BLR = 0xd63f0000,
|
| /src/external/gpl3/gdb/dist/gdb/arch/ |
| aarch64-insn.h | 70 /* BLR 1101 0110 0011 1111 0000 00rr rrr0 0000 */
72 BLR = 0xd63f0000,
|
| /src/sys/external/bsd/sljit/dist/sljit_src/ |
| sljitNativeARM_64.c | 76 #define BLR 0xd63f0000
1909 PTR_FAIL_IF(push_inst(compiler, ((type >= SLJIT_FAST_CALL) ? BLR : BR) | RN(TMP_REG1)));
1962 return push_inst(compiler, ((type >= SLJIT_FAST_CALL) ? BLR : BR) | RN(src));
1972 return push_inst(compiler, ((type >= SLJIT_FAST_CALL) ? BLR : BR) | RN(TMP_REG1));
|
| sljitNativePPC_common.c | 151 #define BLR (HI(19) | LO(16) | (0x14 << 21))
712 FAIL_IF(push_inst(compiler, BLR));
2063 return push_inst(compiler, BLR);
|
| /src/external/gpl3/binutils/dist/bfd/ |
| elf64-ppc.c | 274 #define BLR 0x4e800020 /* blr */
2754 . .foo: blr
6216 bfd_put_32 (abfd, BLR, p);
6240 bfd_put_32 (abfd, BLR, p);
6255 bfd_put_32 (abfd, BLR, p);
6270 bfd_put_32 (abfd, BLR, p);
6287 bfd_put_32 (abfd, BLR, p);
6311 bfd_put_32 (abfd, BLR, p);
6319 bfd_put_32 (abfd, BLR, p)
[all...] |
| /src/external/gpl3/binutils.old/dist/bfd/ |
| elf64-ppc.c | 274 #define BLR 0x4e800020 /* blr */
2762 . .foo: blr
6216 bfd_put_32 (abfd, BLR, p);
6240 bfd_put_32 (abfd, BLR, p);
6255 bfd_put_32 (abfd, BLR, p);
6270 bfd_put_32 (abfd, BLR, p);
6287 bfd_put_32 (abfd, BLR, p);
6311 bfd_put_32 (abfd, BLR, p);
6319 bfd_put_32 (abfd, BLR, p)
[all...] |
| /src/external/gpl3/gdb.old/dist/bfd/ |
| elf64-ppc.c | 274 #define BLR 0x4e800020 /* blr */
2762 . .foo: blr
6209 bfd_put_32 (abfd, BLR, p);
6233 bfd_put_32 (abfd, BLR, p);
6248 bfd_put_32 (abfd, BLR, p);
6263 bfd_put_32 (abfd, BLR, p);
6280 bfd_put_32 (abfd, BLR, p);
6304 bfd_put_32 (abfd, BLR, p);
6312 bfd_put_32 (abfd, BLR, p)
[all...] |
| /src/external/gpl3/gdb/dist/bfd/ |
| elf64-ppc.c | 274 #define BLR 0x4e800020 /* blr */
2754 . .foo: blr
6208 bfd_put_32 (abfd, BLR, p);
6232 bfd_put_32 (abfd, BLR, p);
6247 bfd_put_32 (abfd, BLR, p);
6262 bfd_put_32 (abfd, BLR, p);
6279 bfd_put_32 (abfd, BLR, p);
6303 bfd_put_32 (abfd, BLR, p);
6311 bfd_put_32 (abfd, BLR, p)
[all...] |
| /src/sys/arch/hppa/hppa/ |
| db_disasm.c | 550 #define BLR 0x3a, 0x02, 16, 3 /* BRANCH and LINK REGISTER */
1029 { BLR, 0, "blr", brDasm },
|
| /src/external/gpl3/gdb.old/dist/gdb/ |
| aarch64-tdep.c | 3760 if (masked_insn == BLR)
3772 if (masked_insn == RET || masked_insn == BR || masked_insn == BLR)
|
| /src/external/gpl3/gdb.old/dist/gdbserver/ |
| linux-aarch64-low.cc | 1190 /* Write a BLR instruction into *BUF.
1192 BLR rn
1199 return aarch64_emit_insn (buf, BLR | ENCODE (rn.num, 5, 5));
2466 BLR ip0
|
| /src/external/gpl3/gdb/dist/gdbserver/ |
| linux-aarch64-low.cc | 1236 /* Write a BLR instruction into *BUF.
1238 BLR rn
1245 return aarch64_emit_insn (buf, BLR | ENCODE (rn.num, 5, 5));
2512 BLR ip0
|
| /src/external/gpl3/gdb/dist/gdb/ |
| aarch64-tdep.c | 3839 if (masked_insn == BLR)
3857 if (masked_insn == RET || masked_insn == BR || masked_insn == BLR)
|
