| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFISelLowering.h | 29 BR_CC,
|
| BPFISelLowering.cpp | 70 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
125 setOperationAction(ISD::BR_CC, MVT::i32,
283 case ISD::BR_CC:
602 return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS,
634 case BPFISD::BR_CC:
635 return "BPFISD::BR_CC";
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiISelLowering.h | 49 // BR_CC - Used to glue together a conditional branch and comparison
50 BR_CC,
|
| LanaiISelLowering.cpp | 85 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
180 case ISD::BR_CC:
879 return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest,
1110 case LanaiISD::BR_CC:
1111 return "LanaiISD::BR_CC";
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 948 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in
953 BR_CC,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 60 BR_CC,
|
| MSP430ISelLowering.cpp | 89 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
90 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
348 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
1137 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
1378 case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC";
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCISelLowering.cpp | 116 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
204 assert(LHS.getValueType() == MVT::i32 && "Only know how to BR_CC i32");
756 case ISD::BR_CC:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelLowering.cpp | 97 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
98 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
99 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
100 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
800 case ISD::BR_CC:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.h | 39 BR_CC,
|
| RISCVISelLowering.cpp | 173 setOperationAction(ISD::BR_CC, XLenVT, Expand);
317 setOperationAction(ISD::BR_CC, MVT::f16, Expand);
329 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
346 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
2729 return DAG.getNode(RISCVISD::BR_CC, DL, Op.getValueType(), Op.getOperand(0),
2733 return DAG.getNode(RISCVISD::BR_CC, DL, Op.getValueType(), Op.getOperand(0),
5795 case RISCVISD::BR_CC: {
5802 // Fold (br_cc (setlt X, Y), 0, ne, dest) ->
5803 // (br_cc X, Y, lt, dest)
5804 // Sometimes the setcc is introduced after br_cc has been formed
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | 1037 case ISD::BR_CC: {
1042 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 :
3545 // Expand brcond's setcc into its constituent parts and create a BR_CC
3550 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3564 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3705 case ISD::BR_CC: {
3717 assert(Legalized && "Can't legalize BR_CC with legal condition!");
3719 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3722 assert(!NeedInvert && "Don't know how to invert BR_CC!");
3724 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1
[all...] |
| SelectionDAGDumper.cpp | 376 case ISD::BR_CC: return "br_cc";
|
| LegalizeFloatTypes.cpp | 814 case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N); break;
1767 case ISD::BR_CC: Res = ExpandFloatOp_BR_CC(N); break;
1803 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 1543 // Sparc doesn't have BRCOND either, it has BR_CC.
1547 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1548 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1549 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1550 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
1571 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
2444 // If this is a br_cc of a "setcc", and if the setcc got lowered into
3034 case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 1611 // Expand BR_CC and SELECT_CC for all integer and fp types.
1613 setOperationAction(ISD::BR_CC, VT, Expand);
1617 setOperationAction(ISD::BR_CC, VT, Expand);
1620 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
1644 ISD::BR_CC, ISD::SELECT_CC, ISD::ConstantPool,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 400 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
401 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
402 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
403 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 122 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
123 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
|
| SIISelLowering.cpp | 222 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
223 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
224 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
225 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
226 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
523 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
561 setOperationAction(ISD::BR_CC, MVT::f16, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 91 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 382 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
383 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
384 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
385 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
386 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
436 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
611 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
648 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
676 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
978 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 792 setTargetDAGCombine(ISD::BR_CC);
1376 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1378 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1379 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1380 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
9855 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
16594 assert(N->getOpcode() == ISD::BR_CC && "Expected BRCOND or BR_CC!");
16964 case ISD::BR_CC: return PerformHWLoopCombine(N, DCI, Subtarget);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.cpp | 124 setOperationAction(ISD::BR_CC, VT, Expand);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEISelLowering.cpp | 2487 case ISD::BR_CC:
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 253 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
|
