| /src/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| c_dsp32shiftim_rot.s | 20 R0 = ROT R0 BY 1;
21 R1 = ROT R1 BY 5;
22 R2 = ROT R2 BY 9;
23 R3 = ROT R3 BY 8;
24 R4 = ROT R4 BY 24;
25 R5 = ROT R5 BY 31;
26 R6 = ROT R6 BY 14;
27 R7 = ROT R7 BY 25;
45 R6 = ROT R0 BY -3;
46 R7 = ROT R1 BY -9
[all...] |
| c_dsp32shift_lhh.s | 11 // d_reg = lshift/lshift (d BY d_lo)
12 // Rx by RLx
21 R1 = LSHIFT R0 BY R0.L (V);
22 R2 = LSHIFT R1 BY R0.L (V);
23 R3 = LSHIFT R2 BY R0.L (V);
24 R4 = LSHIFT R3 BY R0.L (V);
25 R5 = LSHIFT R4 BY R0.L (V);
26 R6 = LSHIFT R5 BY R0.L (V);
27 R7 = LSHIFT R6 BY R0.L (V);
28 R0 = LSHIFT R7 BY R0.L (V)
[all...] |
| c_dsp32shift_amix.s | 20 R4.H = ASHIFT R0.H BY R1.L;
21 R4.L = ASHIFT R0.L BY R1.L; /* r4 = 0x00020002 */
22 R5.H = ASHIFT R2.H BY R3.L;
23 R5.L = ASHIFT R2.L BY R3.L; /* r5 = 0x00080008 */
24 R6 = ASHIFT R0 BY R1.L (V); /* r6 = 0x00020002 */
25 R7 = ASHIFT R2 BY R3.L (V); /* r7 = 0x00080008 */
34 R6 = ASHIFT R0 BY R1.L; /* r6 = 0x00080010 */
35 R7 = ASHIFT R2 BY R3.L;
42 A0 = ASHIFT A0 BY R1.L; /* a0 = 0x00080008 */
48 R5 = ASHIFT R4 BY R1.L; /* r5 = 0x60000006 *
[all...] |
| c_dsp32shift_af.s | 9 // d_reg = ashift (d BY d_lo)
10 // Rx by RLx
19 R4 = ASHIFT R0 BY R0.L;
20 R5 = ASHIFT R1 BY R0.L;
21 R6 = ASHIFT R2 BY R0.L;
22 R7 = ASHIFT R3 BY R0.L;
37 R5 = ASHIFT R0 BY R1.L;
38 R6 = ASHIFT R1 BY R1.L;
39 R7 = ASHIFT R2 BY R1.L;
40 R4 = ASHIFT R3 BY R1.L
[all...] |
| c_dsp32shift_lmix.s | 20 R4.H = LSHIFT R0.H BY R1.L;
21 R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x00020002 */
22 R5.H = LSHIFT R2.H BY R3.L;
23 R5.L = LSHIFT R2.L BY R3.L; /* r5 = 0x00080008 */
24 R6 = LSHIFT R0 BY R1.L (V); /* r6 = 0x00020002 */
25 R7 = LSHIFT R2 BY R3.L (V); /* r7 = 0x00080008 */
34 R6 = LSHIFT R0 BY R1.L; /* r6 = 0x00080010 */
35 R7 = LSHIFT R2 BY R3.L;
42 A0 = LSHIFT A0 BY R1.L; /* a0 = 0x00080008 */
48 R6 = LSHIFT R4 BY R1.L; /* r5 = 0x60000006 *
[all...] |
| c_dsp32shift_rot_mix.s | 20 R1 = ROT R0 BY R0.L;
21 R2 = ROT R1 BY R0.L;
22 R3 = ROT R2 BY R0.L;
23 R4 = ROT R3 BY R0.L;
24 R5 = ROT R4 BY R0.L;
25 R6 = ROT R5 BY R0.L;
26 R7 = ROT R6 BY R0.L;
27 R0 = ROT R7 BY R0.L;
40 A0 = ROT A0 BY R1.L;
44 R7 = ROT R4 BY R1.L
[all...] |
| c_dsp32shift_ahh.s | 11 // d_reg = ashift/ashift (d BY d_lo)
12 // Rx by RLx
21 R5 = ASHIFT R0 BY R0.L (V);
22 R0 = ASHIFT R1 BY R0.L (V);
23 R1 = ASHIFT R2 BY R0.L (V);
24 R2 = ASHIFT R3 BY R0.L (V);
25 R3 = ASHIFT R4 BY R0.L (V);
26 R4 = ASHIFT R5 BY R0.L (V);
27 R7 = ASHIFT R6 BY R0.L (V);
28 R6 = ASHIFT R7 BY R0.L (V)
[all...] |
| c_dsp32shift_ahh_s.s | 11 // d_reg = ashift/ashift (d BY d_lo) saturation
12 // Rx by RLx
21 R5 = ASHIFT R0 BY R0.L (V , S);
22 R0 = ASHIFT R1 BY R0.L (V , S);
23 R1 = ASHIFT R2 BY R0.L (V , S);
24 R2 = ASHIFT R3 BY R0.L (V , S);
25 R3 = ASHIFT R4 BY R0.L (V , S);
26 R4 = ASHIFT R5 BY R0.L (V , S);
27 R7 = ASHIFT R6 BY R0.L (V , S);
28 R6 = ASHIFT R7 BY R0.L (V , S)
[all...] |
| c_dsp32shift_rot.s | 20 R1 = ROT R0 BY R0.L;
21 R2 = ROT R1 BY R0.L;
22 R3 = ROT R2 BY R0.L;
23 R4 = ROT R3 BY R0.L;
24 R5 = ROT R4 BY R0.L;
25 R6 = ROT R5 BY R0.L;
26 R7 = ROT R6 BY R0.L;
27 R0 = ROT R7 BY R0.L;
46 R2 = ROT R0 BY R1.L;
47 R3 = ROT R1 BY R1.L
[all...] |
| c_dsp32shift_ahalf_ln.s | 12 // d_lo = ashft (d_lo BY d_lo)
13 // RLx by RLx
22 R0.L = ASHIFT R0.L BY R0.L;
23 R1.L = ASHIFT R1.L BY R0.L;
24 R2.L = ASHIFT R2.L BY R0.L;
25 R3.L = ASHIFT R3.L BY R0.L;
26 R4.L = ASHIFT R4.L BY R0.L;
27 R5.L = ASHIFT R5.L BY R0.L;
28 R6.L = ASHIFT R6.L BY R0.L;
29 R7.L = ASHIFT R7.L BY R0.L
[all...] |
| c_dsp32shift_ahalf_lp.s | 11 // d_lo = ashft (d_lo BY d_lo)
12 // RLx by RLx
21 R0.L = ASHIFT R0.L BY R0.L;
22 R1.L = ASHIFT R1.L BY R0.L;
23 R2.L = ASHIFT R2.L BY R0.L;
24 R3.L = ASHIFT R3.L BY R0.L;
25 R4.L = ASHIFT R4.L BY R0.L;
26 R5.L = ASHIFT R5.L BY R0.L;
27 R6.L = ASHIFT R6.L BY R0.L;
28 R7.L = ASHIFT R7.L BY R0.L
[all...] |
| c_dsp32shift_ahalf_lp_s.s | 11 // d_lo = ashft (d_lo BY d_lo)
12 // RLx by RLx
21 R0.L = ASHIFT R0.L BY R0.L (S);
22 R1.L = ASHIFT R1.L BY R0.L (S);
23 R2.L = ASHIFT R2.L BY R0.L (S);
24 R3.L = ASHIFT R3.L BY R0.L (S);
25 R4.L = ASHIFT R4.L BY R0.L (S);
26 R5.L = ASHIFT R5.L BY R0.L (S);
27 R6.L = ASHIFT R6.L BY R0.L (S);
28 R7.L = ASHIFT R7.L BY R0.L (S)
[all...] |
| c_dsp32shift_lf.s | 11 // d_reg = lshift (d BY d_lo)
12 // Rx by RLx
21 R7 = LSHIFT R0 BY R0.L;
22 R6 = LSHIFT R1 BY R0.L;
23 R0 = LSHIFT R2 BY R0.L;
24 R1 = LSHIFT R3 BY R0.L;
25 R2 = LSHIFT R4 BY R0.L;
26 R3 = LSHIFT R5 BY R0.L;
27 R4 = LSHIFT R6 BY R0.L;
28 R5 = LSHIFT R7 BY R0.L
[all...] |
| c_dsp32shift_lhalf_ln.s | 11 // d_lo = lshift (d_lo BY d_lo)
12 // RLx by RLx
21 R0.L = LSHIFT R0.L BY R0.L;
22 R1.L = LSHIFT R1.L BY R0.L;
23 R2.L = LSHIFT R2.L BY R0.L;
24 R3.L = LSHIFT R3.L BY R0.L;
25 R4.L = LSHIFT R4.L BY R0.L;
26 R5.L = LSHIFT R5.L BY R0.L;
27 R6.L = LSHIFT R6.L BY R0.L;
28 R7.L = LSHIFT R7.L BY R0.L
[all...] |
| c_dsp32shift_lhalf_lp.s | 11 // d_lo = lshift (d_lo BY d_lo)
12 // RLx by RLx
21 R0.L = LSHIFT R0.L BY R0.L;
22 R1.L = LSHIFT R1.L BY R0.L;
23 R2.L = LSHIFT R2.L BY R0.L;
24 R3.L = LSHIFT R3.L BY R0.L;
25 R4.L = LSHIFT R4.L BY R0.L;
26 R5.L = LSHIFT R5.L BY R0.L;
27 R6.L = LSHIFT R6.L BY R0.L;
28 R7.L = LSHIFT R7.L BY R0.L
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/ |
| c_dsp32shiftim_rot.s | 20 R0 = ROT R0 BY 1;
21 R1 = ROT R1 BY 5;
22 R2 = ROT R2 BY 9;
23 R3 = ROT R3 BY 8;
24 R4 = ROT R4 BY 24;
25 R5 = ROT R5 BY 31;
26 R6 = ROT R6 BY 14;
27 R7 = ROT R7 BY 25;
45 R6 = ROT R0 BY -3;
46 R7 = ROT R1 BY -9
[all...] |
| c_dsp32shift_lhh.s | 11 // d_reg = lshift/lshift (d BY d_lo)
12 // Rx by RLx
21 R1 = LSHIFT R0 BY R0.L (V);
22 R2 = LSHIFT R1 BY R0.L (V);
23 R3 = LSHIFT R2 BY R0.L (V);
24 R4 = LSHIFT R3 BY R0.L (V);
25 R5 = LSHIFT R4 BY R0.L (V);
26 R6 = LSHIFT R5 BY R0.L (V);
27 R7 = LSHIFT R6 BY R0.L (V);
28 R0 = LSHIFT R7 BY R0.L (V)
[all...] |
| c_dsp32shift_amix.s | 20 R4.H = ASHIFT R0.H BY R1.L;
21 R4.L = ASHIFT R0.L BY R1.L; /* r4 = 0x00020002 */
22 R5.H = ASHIFT R2.H BY R3.L;
23 R5.L = ASHIFT R2.L BY R3.L; /* r5 = 0x00080008 */
24 R6 = ASHIFT R0 BY R1.L (V); /* r6 = 0x00020002 */
25 R7 = ASHIFT R2 BY R3.L (V); /* r7 = 0x00080008 */
34 R6 = ASHIFT R0 BY R1.L; /* r6 = 0x00080010 */
35 R7 = ASHIFT R2 BY R3.L;
42 A0 = ASHIFT A0 BY R1.L; /* a0 = 0x00080008 */
48 R5 = ASHIFT R4 BY R1.L; /* r5 = 0x60000006 *
[all...] |
| c_dsp32shift_af.s | 9 // d_reg = ashift (d BY d_lo)
10 // Rx by RLx
19 R4 = ASHIFT R0 BY R0.L;
20 R5 = ASHIFT R1 BY R0.L;
21 R6 = ASHIFT R2 BY R0.L;
22 R7 = ASHIFT R3 BY R0.L;
37 R5 = ASHIFT R0 BY R1.L;
38 R6 = ASHIFT R1 BY R1.L;
39 R7 = ASHIFT R2 BY R1.L;
40 R4 = ASHIFT R3 BY R1.L
[all...] |
| c_dsp32shift_lmix.s | 20 R4.H = LSHIFT R0.H BY R1.L;
21 R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x00020002 */
22 R5.H = LSHIFT R2.H BY R3.L;
23 R5.L = LSHIFT R2.L BY R3.L; /* r5 = 0x00080008 */
24 R6 = LSHIFT R0 BY R1.L (V); /* r6 = 0x00020002 */
25 R7 = LSHIFT R2 BY R3.L (V); /* r7 = 0x00080008 */
34 R6 = LSHIFT R0 BY R1.L; /* r6 = 0x00080010 */
35 R7 = LSHIFT R2 BY R3.L;
42 A0 = LSHIFT A0 BY R1.L; /* a0 = 0x00080008 */
48 R6 = LSHIFT R4 BY R1.L; /* r5 = 0x60000006 *
[all...] |
| c_dsp32shift_rot_mix.s | 20 R1 = ROT R0 BY R0.L;
21 R2 = ROT R1 BY R0.L;
22 R3 = ROT R2 BY R0.L;
23 R4 = ROT R3 BY R0.L;
24 R5 = ROT R4 BY R0.L;
25 R6 = ROT R5 BY R0.L;
26 R7 = ROT R6 BY R0.L;
27 R0 = ROT R7 BY R0.L;
40 A0 = ROT A0 BY R1.L;
44 R7 = ROT R4 BY R1.L
[all...] |
| c_dsp32shift_ahh.s | 11 // d_reg = ashift/ashift (d BY d_lo)
12 // Rx by RLx
21 R5 = ASHIFT R0 BY R0.L (V);
22 R0 = ASHIFT R1 BY R0.L (V);
23 R1 = ASHIFT R2 BY R0.L (V);
24 R2 = ASHIFT R3 BY R0.L (V);
25 R3 = ASHIFT R4 BY R0.L (V);
26 R4 = ASHIFT R5 BY R0.L (V);
27 R7 = ASHIFT R6 BY R0.L (V);
28 R6 = ASHIFT R7 BY R0.L (V)
[all...] |
| c_dsp32shift_ahh_s.s | 11 // d_reg = ashift/ashift (d BY d_lo) saturation
12 // Rx by RLx
21 R5 = ASHIFT R0 BY R0.L (V , S);
22 R0 = ASHIFT R1 BY R0.L (V , S);
23 R1 = ASHIFT R2 BY R0.L (V , S);
24 R2 = ASHIFT R3 BY R0.L (V , S);
25 R3 = ASHIFT R4 BY R0.L (V , S);
26 R4 = ASHIFT R5 BY R0.L (V , S);
27 R7 = ASHIFT R6 BY R0.L (V , S);
28 R6 = ASHIFT R7 BY R0.L (V , S)
[all...] |
| c_dsp32shift_rot.s | 20 R1 = ROT R0 BY R0.L;
21 R2 = ROT R1 BY R0.L;
22 R3 = ROT R2 BY R0.L;
23 R4 = ROT R3 BY R0.L;
24 R5 = ROT R4 BY R0.L;
25 R6 = ROT R5 BY R0.L;
26 R7 = ROT R6 BY R0.L;
27 R0 = ROT R7 BY R0.L;
46 R2 = ROT R0 BY R1.L;
47 R3 = ROT R1 BY R1.L
[all...] |
| c_dsp32shift_ahalf_ln.s | 12 // d_lo = ashft (d_lo BY d_lo)
13 // RLx by RLx
22 R0.L = ASHIFT R0.L BY R0.L;
23 R1.L = ASHIFT R1.L BY R0.L;
24 R2.L = ASHIFT R2.L BY R0.L;
25 R3.L = ASHIFT R3.L BY R0.L;
26 R4.L = ASHIFT R4.L BY R0.L;
27 R5.L = ASHIFT R5.L BY R0.L;
28 R6.L = ASHIFT R6.L BY R0.L;
29 R7.L = ASHIFT R7.L BY R0.L
[all...] |
