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    Searched refs:BankSwizzle (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600InstrInfo.h 60 enum BankSwizzle {
124 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
126 R600InstrInfo::BankSwizzle TransSwz) const;
130 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
132 R600InstrInfo::BankSwizzle TransSwz) const;
135 /// returns true and the first (in lexical order) BankSwizzle affectation
140 /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
145 std::vector<BankSwizzle> &BS,
R600InstrInfo.cpp 352 R600InstrInfo::BankSwizzle Swz) {
379 static unsigned getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) {
408 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
410 R600InstrInfo::BankSwizzle TransSwz) const {
457 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
469 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle;
477 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
479 R600InstrInfo::BankSwizzle TransSwz) const {
492 isConstCompatible(R600InstrInfo::BankSwizzle TransSwz,
514 std::vector<BankSwizzle> &ValidSwizzle
    [all...]
R600Packetizer.cpp 223 std::vector<R600InstrInfo::BankSwizzle> &BS,
261 // Is there a BankSwizzle set that meet Read Port limitations ?
291 std::vector<R600InstrInfo::BankSwizzle> BS;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/
AMDGPUInstPrinter.cpp 1470 int BankSwizzle = MI->getOperand(OpNo).getImm();
1471 switch (BankSwizzle) {

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