| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64StorePairSuppress.cpp | 150 const MachineOperand *BaseOp;
153 if (TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable,
155 BaseOp->isReg()) {
156 Register BaseReg = BaseOp->getReg();
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| AArch64InstrInfo.h | 137 const MachineOperand *&BaseOp,
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| AArch64InstrInfo.cpp | 2520 const MachineOperand *BaseOp;
2521 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, OffsetIsScalable,
2524 BaseOps.push_back(BaseOp);
2547 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset,
2579 BaseOp = &LdSt.getOperand(1);
2583 BaseOp = &LdSt.getOperand(2);
2588 if (!BaseOp->isReg() && !BaseOp->isFI())
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| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 107 static bool getBaseOffset(const MachineInstr &MI, const MachineOperand *&BaseOp,
127 BaseOp = &MI.getOperand(1);
139 BaseOp = &MI.getOperand(1);
144 BaseOp = &MI.getOperand(2);
158 BaseOp = &MI.getOperand(1);
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| ARMLoadStoreOptimizer.cpp | 1291 const MachineOperand &BaseOP = MI->getOperand(0);
1292 Register Base = BaseOP.getReg();
1293 bool BaseKill = BaseOP.isKill();
1621 const MachineOperand &BaseOp = MI.getOperand(2);
1622 Register Base = BaseOp.getReg();
1652 MIB.add(Reg0Op).add(Reg1Op).addReg(BaseOp.getReg(), RegState::Define);
1655 MIB.addReg(BaseOp.getReg(), RegState::Define).add(Reg0Op).add(Reg1Op);
1657 MIB.addReg(BaseOp.getReg(), RegState::Kill)
1767 const MachineOperand &BaseOp = MI->getOperand(2);
1768 Register BaseReg = BaseOp.getReg()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonOptAddrMode.cpp | 363 MachineOperand BaseOp = MID.mayLoad() ? MI->getOperand(1)
366 if (!BaseOp.isReg() || BaseOp.getReg() != AddDefR)
418 MachineOperand &BaseOp = MID.mayLoad() ? UseMI->getOperand(1)
422 BaseOp.setReg(newReg);
423 BaseOp.setIsUndef(AddRegOp.isUndef());
424 BaseOp.setImplicit(AddRegOp.isImplicit());
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| HexagonInstrInfo.cpp | 1086 const MachineOperand &BaseOp = MI.getOperand(1);
1087 assert(BaseOp.getSubReg() == 0);
1093 .addReg(BaseOp.getReg(), getRegState(BaseOp))
1101 const MachineOperand &BaseOp = MI.getOperand(1);
1102 assert(BaseOp.getSubReg() == 0);
1110 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill)
1115 .addReg(BaseOp.getReg(), getRegState(BaseOp))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiInstrInfo.h | 77 const MachineOperand *&BaseOp,
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| LanaiInstrInfo.cpp | 758 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset,
789 BaseOp = &LdSt.getOperand(1);
792 if (!BaseOp->isReg())
814 const MachineOperand *BaseOp;
816 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI))
818 BaseOps.push_back(BaseOp);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVInstrInfo.h | 96 const MachineOperand *&BaseOp,
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| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFMISimplifyPatchable.cpp | 96 const MachineOperand *BaseOp = (RelocOp == Op1) ? Op2 : Op1;
139 .add(DefInst->getOperand(0)).addImm(Opcode).add(*BaseOp)
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| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetInstrInfo.cpp | 1072 const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset,
1080 BaseOp = BaseOps.front();
1224 const MachineOperand *BaseOp;
1225 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable,
1249 return ParamLoadedValue(*BaseOp, Expr);
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| MachineSink.cpp | 1007 const MachineOperand *BaseOp;
1010 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI))
1013 if (!BaseOp->isReg())
1026 MBP.LHS.getReg() == BaseOp->getReg();
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| ModuloSchedule.cpp | 913 const MachineOperand *BaseOp;
916 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI))
923 if (!BaseOp->isReg())
926 Register BaseReg = BaseOp->getReg();
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| MachinePipeliner.cpp | 2127 const MachineOperand *BaseOp;
2130 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI))
2137 if (!BaseOp->isReg())
2140 Register BaseReg = BaseOp->getReg();
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIInstrInfo.cpp | 253 const MachineOperand *BaseOp, *OffsetOp;
257 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr);
261 if (!BaseOp) {
263 // TODO: find the implicit use operand for M0 and use that as BaseOp?
266 BaseOps.push_back(BaseOp);
302 BaseOps.push_back(BaseOp);
323 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
324 if (BaseOp && !BaseOp->isFI())
325 BaseOps.push_back(BaseOp);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.h | 533 const MachineOperand *&BaseOp,
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| PPCInstrInfo.cpp | 2740 const MachineOperand *BaseOp;
2742 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI))
2744 BaseOps.push_back(BaseOp);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelLowering.cpp | 1375 unsigned BaseOp = 0;
1382 BaseOp = M68kISD::ADD;
1386 BaseOp = M68kISD::ADD;
1390 BaseOp = M68kISD::SUB;
1394 BaseOp = M68kISD::SUB;
1401 SDValue Arith = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
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| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| TargetInstrInfo.h | 1320 const MachineOperand *&BaseOp, int64_t &Offset,
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| LegalizerHelper.cpp | 6507 unsigned BaseOp;
6514 BaseOp = TargetOpcode::G_ADD;
6519 BaseOp = TargetOpcode::G_ADD;
6524 BaseOp = TargetOpcode::G_SUB;
6529 BaseOp = TargetOpcode::G_SUB;
6563 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, RHSClamped});
6569 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, Min});
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| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | 3678 auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg);
3679 if (!BaseOp.isReg()) // Can be an MO_FrameIndex
3688 AM.BaseReg = BaseOp.getReg();
3746 const MachineOperand *BaseOp =
3748 if (!BaseOp->isReg()) // Can be an MO_FrameIndex
3766 if (!BaseOp->isReg())
3775 BaseOps.push_back(BaseOp);
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| X86ISelLowering.cpp | 23536 unsigned BaseOp = 0;
23541 BaseOp = X86ISD::ADD;
23545 BaseOp = X86ISD::ADD;
23549 BaseOp = X86ISD::SUB;
23553 BaseOp = X86ISD::SUB;
23557 BaseOp = X86ISD::SMUL;
23561 BaseOp = X86ISD::UMUL;
23566 if (BaseOp) {
23569 Value = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 3669 unsigned BaseOp = 0;
3676 BaseOp = SystemZISD::SADDO;
3681 BaseOp = SystemZISD::SSUBO;
3686 BaseOp = SystemZISD::UADDO;
3691 BaseOp = SystemZISD::USUBO;
3698 SDValue Result = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
3734 unsigned BaseOp = 0;
3744 BaseOp = SystemZISD::ADDCARRY;
3752 BaseOp = SystemZISD::SUBCARRY;
3764 SDValue Result = DAG.getNode(BaseOp, DL, VTs, LHS, RHS, Carry)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 5738 const MCOperand &BaseOp = Inst.getOperand(2);
5740 if (BaseOp.isImm()) {
5741 int64_t ImmValue = BaseOp.getImm();
5752 if (expandLoadAddress(ATReg, BaseReg, BaseOp, !isGP64bit(), IDLoc, Out, STI))
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