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    Searched refs:BaseOpcode (Results 1 - 17 of 17) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstrInfo.h 52 unsigned BaseOpcode;
79 const ImageDimIntrinsicInfo *getImageDimInstrinsicByBaseOpcode(unsigned BaseOpcode,
AMDGPUInstructionSelector.cpp 1469 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
1470 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode);
1474 AMDGPU::getMIMGLZMappingInfo(Intr->BaseOpcode);
1476 AMDGPU::getMIMGMIPMappingInfo(Intr->BaseOpcode);
1477 unsigned IntrOpcode = Intr->BaseOpcode;
1488 if (!BaseOpcode->Sampler)
1511 if (BaseOpcode->Atomic) {
1517 const bool Is64Bit = BaseOpcode->AtomicX2 ?
1521 if (BaseOpcode->AtomicX2) {
1532 DMaskLanes = BaseOpcode->Gather4 ? 4 : countPopulation(DMask)
    [all...]
AMDGPULegalizerInfo.cpp 4123 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
4124 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode);
4142 if (!BaseOpcode->Atomic) {
4144 if (BaseOpcode->Gather4) {
4148 } else if (!IsTFE && !BaseOpcode->Store) {
4173 if (BaseOpcode->Atomic) {
4181 if (BaseOpcode->AtomicX2) {
4195 AMDGPU::getMIMGLZMappingInfo(Intr->BaseOpcode)) {
4218 if (AMDGPU::getMIMGMIPMappingInfo(Intr->BaseOpcode)) {
4232 if (BaseOpcode->Gradients && !ST.hasG16() && (IsA16 != IsG16))
    [all...]
SIISelLowering.cpp 1045 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
1046 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode);
1048 if (!BaseOpcode->Gather4) {
5964 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
5965 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode);
5968 AMDGPU::getMIMGLZMappingInfo(Intr->BaseOpcode);
5970 AMDGPU::getMIMGMIPMappingInfo(Intr->BaseOpcode);
5971 unsigned IntrOpcode = Intr->BaseOpcode;
5989 if (BaseOpcode->Atomic) {
5993 if (BaseOpcode->AtomicX2)
    [all...]
SIShrinkInstructions.cpp 287 AMDGPU::getMIMGOpcode(Info->BaseOpcode, AMDGPU::MIMGEncGfx10Default,
SILoadStoreOptimizer.cpp 405 return Info->BaseOpcode;
450 if (Info && AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode)->Sampler)
SIInsertWaitcnts.cpp 160 return AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode)->Sampler
SIInstrInfo.cpp 4204 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
4205 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
4226 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, ST.hasG16());
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstrFMA3Info.cpp 132 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
137 ((BaseOpcode >= 0x96 && BaseOpcode <= 0x9F) ||
138 (BaseOpcode >= 0xA6 && BaseOpcode <= 0xAF) ||
139 (BaseOpcode >= 0xB6 && BaseOpcode <= 0xBF));
156 unsigned FormIndex = ((BaseOpcode - 0x90) >> 4) & 0x3;
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86MCCodeEmitter.cpp 1438 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
1441 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
1456 emitByte(BaseOpcode, OS);
1465 emitByte(BaseOpcode + OpcodeOffset, OS);
1477 emitByte(BaseOpcode, OS);
1484 emitByte(BaseOpcode, OS);
1492 emitByte(BaseOpcode, OS);
1501 emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++)), OS);
1505 emitByte(BaseOpcode, OS);
1521 emitByte(BaseOpcode, OS)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/
AMDGPUBaseInfo.cpp 138 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
140 const MIMGInfo *Info = getMIMGOpcodeHelper(BaseOpcode, MIMGEncoding,
147 return Info ? getMIMGBaseOpcodeInfo(Info->BaseOpcode) : nullptr;
153 getMIMGOpcodeHelper(OrigInfo->BaseOpcode, OrigInfo->MIMGEncoding,
158 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
161 unsigned AddrWords = BaseOpcode->NumExtraArgs;
162 unsigned AddrComponents = (BaseOpcode->Coordinates ? Dim->NumCoords : 0) +
163 (BaseOpcode->LodOrClampOrMip ? 1 : 0);
174 if (BaseOpcode->Gradients) {
175 if ((IsA16 && !IsG16Supported) || BaseOpcode->G16
    [all...]
AMDGPUBaseInfo.h 281 MIMGBaseOpcode BaseOpcode;
298 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
344 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
351 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
357 uint16_t BaseOpcode;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/
AMDGPUDisassembler.cpp 720 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
721 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
727 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI));
759 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
AMDGPUAsmParser.cpp 3419 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
3420 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
3442 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, DimInfo, IsA16, hasG16());
3501 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
3502 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
3504 if (!BaseOpcode->MSAA)
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 9652 unsigned BaseOpcode = 0;
9655 case ISD::VECREDUCE_FADD: BaseOpcode = ISD::FADD; break;
9656 case ISD::VECREDUCE_FMUL: BaseOpcode = ISD::FMUL; break;
9657 case ISD::VECREDUCE_MUL: BaseOpcode = ISD::MUL; break;
9658 case ISD::VECREDUCE_AND: BaseOpcode = ISD::AND; break;
9659 case ISD::VECREDUCE_OR: BaseOpcode = ISD::OR; break;
9660 case ISD::VECREDUCE_XOR: BaseOpcode = ISD::XOR; break;
9661 case ISD::VECREDUCE_FMAX: BaseOpcode = ISD::FMAXNUM; break;
9662 case ISD::VECREDUCE_FMIN: BaseOpcode = ISD::FMINNUM; break;
9680 Op0 = DAG.getNode(BaseOpcode, dl, VT, Op0, Rev)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
TargetLowering.cpp 8517 unsigned BaseOpcode = ISD::getVecReduceBaseOpcode(Node->getOpcode());
8529 if (!isOperationLegalOrCustom(BaseOpcode, HalfVT))
8534 Op = DAG.getNode(BaseOpcode, dl, HalfVT, Lo, Hi);
8547 Res = DAG.getNode(BaseOpcode, dl, EltVT, Res, Ops[i], Node->getFlags());
8573 unsigned BaseOpcode = ISD::getVecReduceBaseOpcode(Node->getOpcode());
8577 Res = DAG.getNode(BaseOpcode, dl, EltVT, Res, Ops[i], Flags);
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 3615 unsigned BaseOpcode = ISD::getVecReduceBaseOpcode(Opcode);
3627 DAG.getNeutralElement(BaseOpcode, DL, EltVT, Flags));
3630 DAG.getNeutralElement(BaseOpcode, DL, EltVT, Flags));

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