| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCRegisterInfo.cpp | 46 unsigned BaseReg = FrameReg;
51 .addReg(BaseReg)
60 BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass);
61 if (!BaseReg) {
66 BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj);
67 assert(BaseReg && "Register scavenging failed.");
68 LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI)
72 RS->setRegUsed(BaseReg);
76 .addReg(BaseReg, RegState::Define)
94 .addReg(BaseReg, KillState
[all...] |
| ARCOptAddrMode.cpp | 88 // to accomodate increment of register \p BaseReg by \p Incr
90 MachineOperand &Incr, unsigned BaseReg);
93 // of \p BaseReg by \p Offset
94 void fixPastUses(ArrayRef<MachineInstr *> Uses, unsigned BaseReg,
287 Register BaseReg = Ldst->getOperand(BasePos).getReg();
297 if (Add->getOperand(0).getReg() == StReg || BaseReg == StReg) {
305 for (MachineInstr &MI : MRI->use_nodbg_instructions(BaseReg)) {
343 MachineOperand &Incr, unsigned BaseReg) {
449 Register BaseReg = Ldst.getOperand(BasePos).getReg();
463 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| LocalStackSlotAllocation.cpp | 269 lookupCandidateBaseReg(unsigned BaseReg,
278 return TRI->isFrameOffsetLegal(&MI, BaseReg, Offset);
343 unsigned BaseReg = 0;
387 lookupCandidateBaseReg(BaseReg, BaseOffset, FrameSizeAdjust,
389 LLVM_DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n");
406 BaseReg, BaseOffset, FrameSizeAdjust,
415 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
424 BaseReg = TRI->materializeFrameBaseRegister(Entry, FrameIdx, InstrOffset);
426 LLVM_DEBUG(dbgs() << " into " << printReg(BaseReg, TRI) << '\n');
436 assert(BaseReg != 0 && "Unable to allocate virtual base register!")
[all...] |
| ImplicitNullChecks.cpp | 380 const Register BaseReg = AddrMode.BaseReg, ScaledReg = AddrMode.ScaledReg;
385 if (BaseReg != PointerReg && ScaledReg != PointerReg)
389 // Bail out of the sizes of BaseReg, ScaledReg and PointerReg are not the
391 if ((BaseReg &&
392 TRI->getRegSizeInBits(BaseReg, MRI) != PointerRegSizeInBits) ||
403 // ScaledReg is %rdi, while there is no BaseReg.
451 if (CalculateDisplacementFromAddrMode(BaseReg, 1))
461 if ((BaseReg && BaseReg != PointerReg && !BaseRegIsConstVal) |
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ThumbRegisterInfo.cpp | 120 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
125 const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes,
131 (BaseReg != 0 && !isARMLowRegister(BaseReg));
143 assert(BaseReg == ARM::SP && "Unexpected!");
175 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
177 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
182 /// a destreg = basereg + immediate in Thumb code. Tries a series of ADDs or
188 Register BaseReg, int NumBytes,
208 // DestReg and BaseReg are low, high or the stack pointer
[all...] |
| ThumbRegisterInfo.h | 52 void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
|
| Thumb2InstrInfo.cpp | 278 Register BaseReg, int NumBytes,
282 if (NumBytes == 0 && DestReg != BaseReg) {
284 .addReg(BaseReg, RegState::Kill)
294 if (DestReg != ARM::SP && DestReg != BaseReg &&
316 .addReg(BaseReg)
323 // know anything about BaseReg. t2ADDrr is an invalid
326 // do not generate invalid encoding, put BaseReg first.
328 .addReg(BaseReg)
341 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
344 .addReg(BaseReg)
[all...] |
| Thumb2SizeReduction.cpp | 151 // ARM::t2STMIA (with no basereg writeback) has no Thumb1 equivalent.
499 Register BaseReg = MI->getOperand(0).getReg();
500 assert(isARMLowRegister(BaseReg));
506 if (MI->getOperand(i).getReg() == BaseReg) {
529 Register BaseReg = MI->getOperand(0).getReg();
531 if (MI->getOperand(i).getReg() == BaseReg)
537 Register BaseReg = MI->getOperand(1).getReg();
538 if (BaseReg != ARM::SP)
550 Register BaseReg = MI->getOperand(1).getReg();
551 if (BaseReg == ARM::SP &
[all...] |
| ARMBaseRegisterInfo.cpp | 641 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
660 Register BaseReg = MRI.createVirtualRegister(&ARM::GPRRegClass);
661 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
663 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
669 return BaseReg;
672 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg,
691 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
694 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII, this);
701 Register BaseReg,
742 NumBits = (BaseReg == ARM::SP ? 8 : 5)
[all...] |
| ARMBaseRegisterInfo.h | 173 void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
175 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86FixupLEAs.cpp | 384 Register BaseReg = Base.getReg();
393 if (BaseReg != 0)
394 BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);
403 if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 &&
404 (DestReg == BaseReg || DestReg == IndexReg)) {
406 if (DestReg != BaseReg)
407 std::swap(BaseReg, IndexReg);
412 .addReg(BaseReg).addReg(IndexReg)
417 .addReg(BaseReg).addReg(IndexReg)
[all...] |
| X86InsertPrefetch.cpp | 82 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg();
84 return (BaseReg == 0 ||
85 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) ||
86 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg)) &&
|
| X86AsmPrinter.cpp | 288 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg);
293 bool HasBaseReg = BaseReg.getReg() != 0;
295 BaseReg.getReg() == X86::RIP)
353 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg);
360 bool HasBaseReg = BaseReg.getReg() != 0;
362 BaseReg.getReg() == X86::RIP)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64StorePairSuppress.cpp | 156 Register BaseReg = BaseOp->getReg();
157 if (PrevBaseReg == BaseReg) {
166 PrevBaseReg = BaseReg;
|
| AArch64RegisterInfo.h | 108 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
112 void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
|
| AArch64FalkorHWPFFix.cpp | 217 Register BaseReg;
646 Register BaseReg = MI.getOperand(BaseRegIdx).getReg();
647 if (BaseReg == AArch64::SP || BaseReg == AArch64::WSP)
652 LI.BaseReg = BaseReg;
662 unsigned Base = TRI->getEncodingValue(LI.BaseReg);
756 NewLdI.BaseReg = ScratchReg;
773 .addReg(LdI.BaseReg)
786 TII->get(AArch64::ORRXrs), LdI.BaseReg)
[all...] |
| AArch64LoadStoreOptimizer.cpp | 176 unsigned BaseReg, int Offset);
1238 Register BaseReg = getLdStBaseOp(LoadMI).getReg();
1263 // it's unnecessary to check if BaseReg is modified by the store itself.
1267 BaseReg == getLdStBaseOp(MI).getReg() && getLdStOffsetOp(MI).isImm() &&
1282 if (!ModifiedRegUnits.available(BaseReg))
1533 Register BaseReg = getLdStBaseOp(FirstMI).getReg();
1602 if (BaseReg == MIBaseReg) {
1681 // If the BaseReg has been modified, then we cannot do the optimization.
1687 if (!ModifiedRegUnits.available(BaseReg))
1753 if (!ModifiedRegUnits.available(BaseReg))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCTargetDesc.h | 51 auto BaseReg = MI.getOperand(0).getReg();
54 if (Op.isReg() && Op.getReg() == BaseReg)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kISelDAGToDAG.cpp | 66 SDValue BaseReg;
93 return BaseType == Base::FrameIndexBase || BaseReg.getNode() != nullptr;
99 return BaseType == Base::RegBase && BaseReg.getNode() != nullptr;
137 if (auto *RegNode = dyn_cast_or_null<RegisterSDNode>(BaseReg.getNode()))
144 BaseReg = Reg;
153 dbgs() << ", BaseReg: ";
154 if (BaseReg.getNode())
155 BaseReg.getNode()->dump();
385 AM.BaseReg = N;
460 AM.BaseReg.getNode() == nullptr && doesDispFitFI(AM))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 426 unsigned BaseReg, IndexReg, TmpReg, Scale;
450 : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0),
459 unsigned getBaseReg() const { return BaseReg; }
653 // If we already have a BaseReg, then assume this is the IndexReg with
655 if (!BaseReg) {
656 BaseReg = TmpReg;
659 ErrMsg = "BaseReg/IndexReg already set!";
714 // If we already have a BaseReg, then assume this is the IndexReg with
716 if (!BaseReg) {
717 BaseReg = TmpReg
[all...] |
| X86Operand.h | 60 unsigned BaseReg;
134 if (Mem.BaseReg)
135 OS << ",BaseReg=" << X86IntelInstPrinter::getRegisterName(Mem.BaseReg);
184 return Mem.BaseReg;
320 return isMem() && Mem.BaseReg != X86::RIP && Mem.BaseReg != X86::EIP;
670 Res->Mem.BaseReg = 0;
686 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
693 assert((SegReg || BaseReg || IndexReg || DefaultBaseReg) &
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/MC/MCParser/ |
| MCTargetAsmParser.h | 44 AOK_IntelExpr // SizeDirective SymDisp [BaseReg + IndexReg * Scale + ImmDisp]
66 StringRef BaseReg;
72 : NeedBracs(false), Imm(0), BaseReg(StringRef()), IndexReg(StringRef()),
74 // [BaseReg + IndexReg * ScaleExpression + OFFSET name + ImmediateExpression]
75 IntelExpr(StringRef baseReg, StringRef indexReg, unsigned scale,
77 : NeedBracs(needBracs), Imm(imm), BaseReg(baseReg), IndexReg(indexReg),
82 bool hasBaseReg() const { return !BaseReg.empty(); }
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/AsmParser/ |
| LanaiAsmParser.cpp | 131 unsigned BaseReg;
173 return Mem.BaseReg;
616 Op->Mem.BaseReg = 0;
624 MorphToMemRegReg(unsigned BaseReg, std::unique_ptr<LanaiOperand> Op,
628 Op->Mem.BaseReg = BaseReg;
636 MorphToMemRegImm(unsigned BaseReg, std::unique_ptr<LanaiOperand> Op,
640 Op->Mem.BaseReg = BaseReg;
909 unsigned BaseReg = 0
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 166 unsigned BaseReg = Base.getReg();
169 if (STI.hasFeature(X86::Mode16Bit) && BaseReg == 0 && IndexReg == 0)
171 if ((BaseReg != 0 &&
172 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) ||
183 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg);
186 if ((BaseReg.getReg() != 0 &&
187 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
191 if (BaseReg.getReg() == X86::EIP) {
205 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg);
208 if ((BaseReg.getReg() != 0 &
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsNaClELFStreamer.cpp | 130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg();
131 emitMask(BaseReg, LoadStoreStackMaskReg, STI);
|
