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  /src/usr.bin/mail/
list.c 677 * Check the "To:", "Cc:", and "Bcc" fields for the pattern.
683 static const char *to_fields[] = { "to", "cc", "bcc", 0 };
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
ARCBranchFinalize.cpp 132 LLVM_DEBUG(dbgs() << "Replacing pseudo branch with Cmp + Bcc\n");
137 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(ARC::Bcc))
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ConditionOptimizer.cpp 152 if (Term->getOpcode() != AArch64::Bcc)
165 // Check if there is any use of NZCV between CMP and Bcc.
293 BuildMI(*MBB, BrMI, BrMI.getDebugLoc(), TII->get(AArch64::Bcc))
AArch64CondBrTuning.cpp 137 return BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(AArch64::Bcc))
AArch64MacroFusion.cpp 21 /// CMN, CMP, TST followed by Bcc
24 if (SecondMI.getOpcode() != AArch64::Bcc)
AArch64RedundantCopyElimination.cpp 141 if (Opc != AArch64::Bcc)
AArch64AsmPrinter.cpp 410 MCInstBuilder(AArch64::Bcc)
435 MCInstBuilder(AArch64::Bcc)
450 MCInstBuilder(AArch64::Bcc)
475 MCInstBuilder(AArch64::Bcc)
499 MCInstBuilder(AArch64::Bcc)
AArch64InstrInfo.h 414 case AArch64::Bcc:
AArch64ConditionalCompares.cpp 708 BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), TII->get(AArch64::Bcc))
AArch64InstrInfo.cpp 67 BCCDisplacementBits("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19),
68 cl::desc("Restrict range of Bcc instructions (DEBUG)"));
166 case AArch64::Bcc:
207 case AArch64::Bcc:
236 case AArch64::Bcc:
330 // If the block ends with a B and a Bcc, handle it.
413 // Regular Bcc
490 // Regular Bcc
491 BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB);
1547 case AArch64::Bcc:
    [all...]
AArch64ExpandPseudoInsts.cpp 223 BuildMI(LoadCmpBB, DL, TII->get(AArch64::Bcc))
AArch64FastISel.cpp 2425 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2431 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2462 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMMCInstLower.cpp 207 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc).addImm(20)
ARMInstructionSelector.cpp 118 unsigned Bcc;
329 STORE_OPCODE(Bcc, Bcc);
1152 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.Bcc))
ARMExpandPseudoInsts.cpp 1640 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
1641 BuildMI(LoadCmpBB, DL, TII->get(Bcc))
1664 BuildMI(StoreBB, DL, TII->get(Bcc))
1761 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
1762 BuildMI(LoadCmpBB, DL, TII->get(Bcc))
1784 BuildMI(StoreBB, DL, TII->get(Bcc))
ARMBaseInstrInfo.h 639 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
ARMFastISel.cpp 1249 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1272 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1310 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
ARMAsmPrinter.cpp 1436 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc)
ARMConstantIslandPass.cpp 755 case ARM::Bcc:
1726 dbgs() << " Invert Bcc condition and swap its destination with "
ARMFrameLowering.cpp 2598 Opcode = Thumb ? ARM::tBcc : ARM::Bcc;
ARMBaseInstrInfo.cpp 489 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
2234 return ARM::Bcc;
ARMISelDAGToDAG.cpp 3891 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
3903 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
ARMISelLowering.cpp 10475 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
10932 TII->get(IsThumb1 ? ARM::tBcc : IsThumb2 ? ARM::t2Bcc : ARM::Bcc))
11431 // bCC copy1MBB
11519 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
11554 // BCC (branch to SinkBB if V0 >= 0)
11592 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
11594 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
11598 // Note: BCC and rsbri will be converted into predicated rsbmi
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
ARMMCTargetDesc.cpp 399 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
406 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 1470 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC1).addMBB(DestMBB);
1472 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC2).addMBB(DestMBB);
1570 // Couldn't optimize. Emit a compare + a Bcc.
1576 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC).addMBB(DestMBB);
1608 // Can't emit TB(N)Z/CB(N)Z. Emit a tst + bcc instead.
1612 auto Bcc = MIB.buildInstr(AArch64::Bcc)
1616 return constrainSelectedInstRegOperands(*Bcc, TII, TRI, RBI);

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