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  /src/sys/external/bsd/acpica/dist/utilities/
utownerid.c 129 * Found a free ID. The actual ID is the bit index plus one,
139 * Construct encoded ID from the index and bit position
141 * Note: Last [j].k (bit 4095) is never used and is marked
196 UINT32 Bit;
229 Bit = (UINT32) 1 << ACPI_MOD_32 (OwnerId);
233 if (AcpiGbl_OwnerIdMask[Index] & Bit)
235 AcpiGbl_OwnerIdMask[Index] ^= Bit;
  /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
CodeTemplate.cpp 70 StringRef getName(ExecutionMode Bit) {
71 assert(isEnumValue(Bit) && "Bit must be a power of two");
72 switch (Bit) {
108 for (const auto Bit : getAllExecutionBits())
109 if ((Execution & Bit) == Bit)
110 Result.push_back(Bit);
  /src/sys/external/bsd/compiler_rt/dist/lib/fuzzer/
FuzzerTracePC.h 239 unsigned Bit = 0;
240 /**/ if (Counter >= 128) Bit = 7;
241 else if (Counter >= 32) Bit = 6;
242 else if (Counter >= 16) Bit = 5;
243 else if (Counter >= 8) Bit = 4;
244 else if (Counter >= 4) Bit = 3;
245 else if (Counter >= 3) Bit = 2;
246 else if (Counter >= 2) Bit = 1;
247 return Bit;
  /src/sys/external/bsd/acpica/dist/tools/examples/
extables.c 358 32-bit PM Timer (V1) : 0
375 [0001] Bit Width : 08
376 [0001] Bit Offset : 00
386 [0001] Bit Width : 20
387 [0001] Bit Offset : 00
393 [0001] Bit Width : 00
394 [0001] Bit Offset : 00
400 [0001] Bit Width : 10
401 [0001] Bit Offset : 00
407 [0001] Bit Width : 0
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  /src/external/apache2/llvm/dist/llvm/include/llvm/IR/
GlobalObject.h 160 void setGlobalObjectFlag(unsigned Bit, bool Val) {
161 unsigned Mask = 1 << Bit;
  /src/external/apache2/llvm/dist/llvm/lib/Frontend/OpenMP/
OMPContext.cpp 89 for (unsigned Bit : ActiveTraits.set_bits()) {
90 TraitProperty Property = TraitProperty(Bit);
137 for (unsigned Bit : VMI0.RequiredTraits.set_bits())
138 if (!VMI1.RequiredTraits.test(Bit))
195 for (unsigned Bit : VMI.RequiredTraits.set_bits()) {
196 TraitProperty Property = TraitProperty(Bit);
278 for (unsigned Bit : VMI.RequiredTraits.set_bits()) {
279 TraitProperty Property = TraitProperty(Bit);
  /src/external/apache2/llvm/dist/clang/utils/TableGen/
ClangSACheckersEmitter.cpp 66 const auto *Bit = dyn_cast<BitInit>(B->getBit(i));
67 if (Bit)
68 Value |= uint64_t(Bit->getValue()) << i;
  /src/external/apache2/llvm/dist/llvm/include/llvm/ADT/
BitVector.h 1 //===- llvm/ADT/BitVector.h - Bit vectors -----------------------*- C++ -*-===//
90 // Encapsulation of a single bit.
156 for (auto Bit : Bits)
157 NumBits += countPopulation(Bit);
161 /// any - Returns true if any bit is set.
163 return any_of(Bits, [](BitWord Bit) { return Bit != 0; });
184 /// find_first_in - Returns the index of the first set / unset bit,
196 // The code below is based on search for the first _set_ bit. If
220 /// find_last_in - Returns the index of the last set bit in the rang
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/TableGen/
Record.h 89 /// a bit set is not an int, but they are convertible.
101 /// 'bit' - Represent a single bit
114 std::string getAsString() const override { return "bit"; }
283 /// We could pack these a bit tighter by not having the IK_FirstXXXInit
366 /// This function is used to implement the bit range
369 /// to use the bit selection operator on this value, null is returned.
397 /// Get the \p Init value of the specified bit.
398 virtual Init *getBit(unsigned Bit) const = 0;
456 Init *getBit(unsigned Bit) const override
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/TableGen/
JSONBackend.cpp 50 } else if (auto *Bit = dyn_cast<BitInit>(&I)) {
51 return Bit->getValue() ? 1 : 0;
TGLexer.h 50 Assert, Bit, Bits, Class, Code, Dag, Def, Defm, Defset, Defvar, ElseKW,
Record.cpp 314 // Can only convert single bit.
355 if (getNumBits() != 1) return nullptr; // Only accept if just one bit!
369 if (auto *Bit = dyn_cast<BitInit>(getBit(i)))
370 Result |= static_cast<int64_t>(Bit->getValue()) << i;
403 if (Init *Bit = getBit(e-i-1))
404 Result += Bit->getAsString();
432 // getBit(0) implicitly converts int and bits<1> values to bit.
472 if (Val != 0 && Val != 1) return nullptr; // Only accept 0 or 1 for a bit!
685 Init *OpInit::getBit(unsigned Bit) const {
688 return VarBitInit::get(const_cast<OpInit*>(this), Bit);
    [all...]
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
X86EVEX2VEXTablesEmitter.cpp 94 if (BitInit *Bit = dyn_cast<BitInit>(B->getBit(i)))
95 Value |= uint64_t(Bit->getValue()) << i;
97 PrintFatalError("Invalid VectSize bit");
DFAEmitter.cpp 335 if (auto *Bit = dyn_cast<BitInit>(NewStateInit->getBit(I))) {
336 if (Bit->getValue())
  /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/Disassembler/
M68kDisassembler.cpp 149 uint16_t Bit = (1 << (16 - B - 1));
150 unsigned IsClear = !(Word & Bit);
187 // We have to read the bits in 16-bit chunks because we read them as
188 // 16-bit words but they're actually written in big-endian. If a read
234 uint16_t Bit = (1 << (15 - B));
235 unsigned IsMasked = !(WordMask & Bit);
236 unsigned IsClear = !(WordValue & Bit);
292 // This is a bit of a hack: we can't generate this table at table-gen time
  /src/external/gpl3/gcc/dist/libgcc/config/avr/
lib1funcs.S 318 ;; Bit n of A is 1 --> C += B << n
329 ;; Carry = n-th bit of A
332 ;; If bit n of A is set, then go add B * 2^n to C
458 1: ;; If bit n of A is set, then add B * 2^n to the result in CC
465 3: ;; A >>= 1: Carry = n-th bit of A
762 0: ;; Shift N-th Bit of B[] into Carry. N = 24 - Loop
765 ;; If the N-th Bit of B[] was set...
974 ;; A helper for some 64-bit multiplications with MUL available
1030 0: ;; Rotate B[] right by 1 and set Carry to the N-th Bit of B[]
1037 ;; If the N-th Bit of B[] was set then..
    [all...]
  /src/external/gpl3/gcc.old/dist/libgcc/config/avr/
lib1funcs.S 313 ;; Bit n of A is 1 --> C += B << n
324 ;; Carry = n-th bit of A
327 ;; If bit n of A is set, then go add B * 2^n to C
453 1: ;; If bit n of A is set, then add B * 2^n to the result in CC
460 3: ;; A >>= 1: Carry = n-th bit of A
757 0: ;; Shift N-th Bit of B[] into Carry. N = 24 - Loop
760 ;; If the N-th Bit of B[] was set...
969 ;; A helper for some 64-bit multiplications with MUL available
1025 0: ;; Rotate B[] right by 1 and set Carry to the N-th Bit of B[]
1032 ;; If the N-th Bit of B[] was set then..
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600Packetizer.cpp 11 /// bit of instructions inside a bundle and substitutes src register with
216 void setIsLastBit(MachineInstr *MI, unsigned Bit) const {
218 MI->getOperand(LastOp).setImm(Bit);
  /src/crypto/external/apache2/openssl/lib/libcrypto/arch/riscv64/
ghash-riscv64.S 165 # Load Xi and bit-reverse it
215 # Load the key (already bit-reversed)
247 # Bit-reverse Xi back and store it
302 # Load Xi and bit-reverse it
308 # Load the key (already bit-reversed)
340 # Bit-reverse Xi back and store it
351 # Load Xi and bit-reverse it
401 # Load the key (already bit-reversed)
410 # Load the input data, bit-reverse them, and XOR them with Xi
491 # Bit-reverse final Xi back and store i
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  /src/external/apache2/llvm/dist/llvm/lib/DebugInfo/DWARF/
DWARFDie.cpp 45 uint64_t Bit = 1ULL << Shift;
46 auto PropName = ApplePropertyString(Bit);
50 OS << format("DW_APPLE_PROPERTY_0x%" PRIx64, Bit);
51 if (!(Val ^= Bit))
  /src/sys/external/bsd/acpica/dist/tools/acpiexec/
aetables.h 431 [025h 0037 1] Bit Width : 08
432 [026h 0038 1] Bit Offset : 00
438 [031h 0049 1] Bit Width : 08
439 [032h 0050 1] Bit Offset : 00
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/IPO/
LowerTypeTests.cpp 156 // allows us to compress the bitset by only storing one bit per aligned
215 unsigned Bit = 0;
217 if (BitAllocs[I] < BitAllocs[Bit])
218 Bit = I;
220 AllocByteOffset = BitAllocs[Bit];
224 BitAllocs[Bit] = ReqSize;
229 AllocMask = 1 << Bit;
434 /// ByteArray: the bit mask to apply to bytes loaded from the byte array.
437 /// Inline: the bit mask to test the address against.
557 /// Build a bit set for TypeId using the object layouts i
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 238 /// - Column 0: The 64-bit opcode variants
239 /// - Column 1: The 32-bit opcode variants
269 /// \p DefReg and \p SrcReg are expected to be 32-bit scalar registers.
275 /// \p Dst is expected to be a 32-bit scalar register.
287 /// Emit a TB(N)Z instruction which tests \p Bit in \p TestReg.
289 /// This will also optimize the test bit instruction when possible.
290 MachineInstr *emitTestBit(Register TestReg, uint64_t Bit, bool IsNegative,
429 /// Returns true if \p MI is guaranteed to have the high-half of a 64-bit
794 "GPRs cannot get more than 64-bit width values");
841 // a 1-bit value with any size of register. The minimum size for a GPR is 3
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/Support/
CommandLine.h 1729 template <class T> static unsigned Bit(const T &V) {
1732 "enum exceeds width of bit vector!");
1749 *Location |= Bit(V);
1755 return (*Location & Bit(V)) != 0;
1765 template <class T> static unsigned Bit(const T &V) {
1768 "enum exceeds width of bit vector!");
1773 template <class T> void addValue(const T &V) { Bits |= Bit(V); }
1777 template <class T> bool isSet(const T &V) { return (Bits & Bit(V)) != 0; }
1781 // bits - A bit vector of command options.
  /src/external/apache2/llvm/dist/llvm/lib/IR/
DebugInfoMetadata.cpp 44 assert(Column < (1u << 16) && "Expected 16-bit column");
229 if (DIFlags Bit = Flags & Flag##NAME) { \
230 SplitFlags.push_back(Bit); \
231 Flags &= ~Bit; \
847 // Multi-bit fields can require special handling. In our case, however, the
848 // only multi-bit field is virtuality, and all its values happen to be
849 // single-bit values, so the right behavior just falls out.
851 if (DISPFlags Bit = Flags & SPFlag##NAME) { \
852 SplitFlags.push_back(Bit); \
853 Flags &= ~Bit; \
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