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    Searched refs:BitMask (Results 1 - 21 of 21) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
BitTracker.h 39 struct BitMask;
287 struct BitTracker::BitMask {
288 BitMask() = default;
289 BitMask(uint16_t b, uint16_t e) : B(b), E(e) {}
317 RegisterCell &insert(const RegisterCell &RC, const BitMask &M);
318 RegisterCell extract(const BitMask &M) const; // Returns a new cell.
465 virtual BitMask mask(Register Reg, unsigned Sub) const;
HexagonBitTracker.h 39 BitTracker::BitMask mask(Register Reg, unsigned Sub) const override;
BitTracker.cpp 215 const BitMask &M) {
235 BT::RegisterCell BT::RegisterCell::extract(const BitMask &M) const {
368 BitMask M = mask(RR.Reg, RR.Sub);
690 RegisterCell Res = RegisterCell::ref(A1).extract(BT::BitMask(B, Last));
703 Res.insert(RegisterCell::ref(A2), BT::BitMask(AtN, AtN+W2-1));
707 BT::BitMask BT::MachineEvaluator::mask(Register Reg, unsigned Sub) const {
711 return BitMask(0, W-1);
752 Res.insert(Src, BitMask(0, WS-1));
1003 BitMask OM = ME.mask(OldRR.Reg, OldRR.Sub);
1004 BitMask NM = ME.mask(NewRR.Reg, NewRR.Sub)
    [all...]
HexagonBitTracker.cpp 89 BT::BitMask HexagonEvaluator::mask(Register Reg, unsigned Sub) const {
101 return IsSubLo ? BT::BitMask(0, RW-1)
102 : BT::BitMask(RW, 2*RW-1);
349 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1));
371 RegisterCell CW = RegisterCell(W0).insert(rc(1), BT::BitMask(0, W1-1));
721 RegisterCell RC = RegisterCell(W0).insert(Ext, BT::BitMask(0, Wd-1));
  /src/external/apache2/llvm/dist/clang/lib/AST/Interp/
Integral.h 143 const T BitMask = (T(1) << T(TruncBits)) - 1;
145 const T ExtMask = ~BitMask;
146 return Integral((V & BitMask) | (Signed && (V & SignBit) ? ExtMask : 0));
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
BypassSlowDivision.cpp 341 // BitMask is inverted to check if the operands are
343 uint64_t BitMask = ~BypassType->getBitMask();
344 Value *AndV = Builder.CreateAnd(OrV, BitMask);
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/IPO/
LowerTypeTests.cpp 435 Constant *BitMask;
591 Value *BitMask = B.CreateShl(ConstantInt::get(BitsType, 1), BitIndex);
592 Value *MaskedBits = B.CreateAnd(Bits, BitMask);
689 B.CreateAnd(Byte, ConstantExpr::getPtrToInt(TIL.BitMask, Int8Ty));
908 /// Returns a pointer to the location in which to store the bitmask, if
949 ExportGlobal("bit_mask", TIL.BitMask);
951 return &TTRes.BitMask;
1024 TIL.BitMask = ImportConstant("bit_mask", TTRes.BitMask, 8, Int8PtrTy);
1160 TIL.BitMask = BAI->MaskGlobal
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
LoopIdiomRecognize.cpp 2081 /// %bitmask = shl i32 1, %bitpos
2086 /// %x.curr.bitmasked = and i32 %x.curr, %bitmask
2098 Value *&BitMask, Value *&BitPos,
2134 m_Value(BitMask),
2141 m_CombineAnd(m_Value(BitMask), m_Power2()))) &&
2142 (BitPos = ConstantExpr::getExactLogBase2(cast<Constant>(BitMask)));
2148 (BitMask = ConstantInt::get(CurrX->getType(), Mask)) &&
2201 /// %bitmask = shl i32 1, %bitpos
2206 /// %x.curr.bitmasked = and i32 %x.curr, %bitmask
2221 /// %bitmask = shl i32 1, %bitpo
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
MachineOperand.cpp 554 unsigned BitMask = Flags.second;
557 // Check if the flag's bitmask has the bits of the current mask set.
558 if ((BitMask & Mask.first) == Mask.first) {
563 // Clear the bits which were serialized from the flag's bitmask.
564 BitMask &= ~(Mask.first);
567 if (BitMask) {
568 // When the resulting flag's bitmask isn't zero, we know that we didn't
572 OS << "<unknown bitmask target flag>";
  /src/external/apache2/llvm/dist/llvm/include/llvm/IR/
ModuleSummaryIndexYAML.h 35 io.mapOptional("BitMask", res.BitMask);
ModuleSummaryIndex.h 931 uint8_t BitMask = 0;
  /src/external/apache2/llvm/dist/llvm/lib/LTO/
LTO.cpp 268 AddUint64(S.TTRes.BitMask);
  /src/external/apache2/llvm/dist/llvm/lib/IR/
AsmWriter.cpp 3033 if (TTRes.BitMask)
3034 // BitMask is uint8_t which causes it to print the corresponding char.
3035 Out << ", bitMask: " << (unsigned)TTRes.BitMask;
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsSEISelLowering.cpp 1535 SDValue BitMask = DAG.getConstant(~BitImm, DL, ResTy);
1537 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp 8746 // .mask bitmask, frame_offset
8747 // bitmask: One bit for each register used.
8755 // Parse the bitmask
8756 const MCExpr *BitMask;
8759 if (Parser.parseExpression(BitMask)) {
8760 reportParseError("expected bitmask value");
8764 if (!BitMask->evaluateAsAbsolute(BitMaskVal)) {
8765 reportParseError("bitmask not an absolute expression");
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelLowering.cpp 11905 /// Try to emit a bitmask instruction for a shuffle.
11907 /// This handles cases where we can model a blend exactly as a bitmask due to
12118 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
12184 // Attempt to lower to a bitmask if we can. Only if not optimizing for size.
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 6748 uint64_t BitMask = 0xff;
6753 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
6754 Val |= BitMask;
6756 } else if ((SplatBits & BitMask) != 0) {
6759 BitMask <<= 8;
  /src/external/apache2/llvm/dist/llvm/lib/Bitcode/Reader/
BitcodeReader.cpp 6073 TypeId.TTRes.BitMask = Record[Slot++];
  /src/external/apache2/llvm/dist/llvm/lib/Bitcode/Writer/
BitcodeWriter.cpp 3782 NameVals.push_back(Summary.TTRes.BitMask);
  /src/external/apache2/llvm/dist/llvm/lib/AsmParser/
LLParser.cpp 8187 /// [',' 'sizeM1' ':' UInt64]? [',' 'bitMask' ':' UInt8]?
8247 TTRes.BitMask = (uint8_t)Val;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 1586 // If NewImm or its bitwise NOT is a shifted mask, it is a bitmask immediate
8075 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
12664 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
12677 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {

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