| /src/external/apache2/llvm/dist/llvm/lib/Transforms/IPO/ |
| Annotation2Metadata.cpp | 59 // Look through bitcast.
60 auto *Bitcast = dyn_cast<ConstantExpr>(OpC->getOperand(0));
61 if (!Bitcast || Bitcast->getOpcode() != Instruction::BitCast)
63 auto *Fn = dyn_cast<Function>(Bitcast->getOperand(0));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86LowerAMXType.cpp | 14 /// load/store <256 x i32> instruction to AMX load/store. If the bitcast can
15 /// not be combined with load/store, we transform the bitcast to amx load/store
94 void combineLoadBitcast(LoadInst *LD, BitCastInst *Bitcast);
95 void combineBitcastStore(BitCastInst *Bitcast, StoreInst *ST);
96 bool transformBitcast(BitCastInst *Bitcast);
165 // %2 = bitcast <256 x i32> %src to x86_amx
169 void X86LowerAMXType::combineLoadBitcast(LoadInst *LD, BitCastInst *Bitcast) {
171 Use &U = *(Bitcast->use_begin());
175 IRBuilder<> Builder(Bitcast);
184 Bitcast->replaceAllUsesWith(NewInst)
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| MCInstrDesc.h | 161 Bitcast,
338 /// Return true if this instruction is a bitcast instruction.
339 bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); }
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUPreLegalizerCombiner.cpp | 143 auto Bitcast = B.buildBitcast({S32}, CvtPk);
147 {MinBoundaryDst.getReg(0), Bitcast.getReg(0), MaxBoundaryDst.getReg(0)},
|
| AMDGPURegisterBankInfo.cpp | 1612 auto Bitcast = B.buildBitcast(S32, Src);
1615 auto ExtLo = B.buildSExtInReg(S32, Bitcast, 16);
1616 auto ShiftHi = B.buildAShr(S32, Bitcast, B.buildConstant(S32, 16));
1620 auto ShiftHi = B.buildLShr(S32, Bitcast, B.buildConstant(S32, 16));
1622 auto ExtLo = B.buildAnd(S32, Bitcast, B.buildConstant(S32, 0xffff));
1627 return std::make_pair(Bitcast.getReg(0), ShiftHi.getReg(0));
2660 // Don't put the bitcast or constant in the loop.
2776 // Don't put the bitcast or constant in the loop.
2820 // Keep the bitcast to the original vector type out of the loop. Doing this
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsLegalizerInfo.cpp | 439 auto Bitcast = MIRBuilder.buildMerge(s64, {Src, C_HiMask.getReg(0)});
445 MIRBuilder.buildFSub(Dst, Bitcast, TwoP52FP);
447 MachineInstrBuilder ResF64 = MIRBuilder.buildFSub(s64, Bitcast, TwoP52FP);
|
| MipsISelLowering.cpp | 2325 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2328 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2332 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2355 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2371 // Bitcast to integer nodes.
2372 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2373 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2389 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2410 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2426 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast i
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
| CodeExtractor.cpp | 539 // outside region bitcast to avoid unnecessary alloca/reload instructions
549 Instruction *Bitcast = cast<Instruction>(U);
550 for (User *BU : Bitcast->users()) {
561 LLVM_DEBUG(dbgs() << "Replace use of extracted region bitcast"
562 << *Bitcast << " in out-of-region lifetime marker "
582 Instruction *Bitcast = cast<Instruction>(U);
583 LifetimeMarkerInfo LMI = getLifetimeMarkers(CEAC, Bitcast, ExitBlock);
585 Bitcasts.push_back(Bitcast);
602 LLVM_DEBUG(dbgs() << "Sinking alloca (via bitcast): " << *AI << "\n");
608 "Unsafe to sink bitcast without lifetime markers")
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Coroutines/ |
| Coroutines.cpp | 105 // bitcast i8* %2 to void(i8*)*
117 auto *Bitcast =
119 return Bitcast;
443 // bitcast and ignore this type mismatch.
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/ |
| LoadStoreVectorizer.cpp | 1252 Value *Bitcast =
1255 Builder.CreateAlignedLoad(VecTy, Bitcast, MaybeAlign(Alignment));
1280 // Bitcast might not be an Instruction, if the value being loaded is a
1282 if (Instruction *BitcastInst = dyn_cast<Instruction>(Bitcast))
1300 if (Instruction *BitcastInst = dyn_cast<Instruction>(Bitcast))
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| LegalizerInfo.cpp | 62 case Bitcast:
63 OS << "Bitcast";
181 case Bitcast: {
579 case Bitcast:
|
| LegalizerHelper.cpp | 126 case Bitcast:
127 LLVM_DEBUG(dbgs() << ".. Bitcast type\n");
128 return bitcast(MI, Step.TypeIdx, Step.NewType);
2434 LLT DstCastTy = DstEltTy; // Intermediate bitcast result type
2540 // v4i32:castx = bitcast x:v2i64
2542 // i64 = bitcast
2857 LegalizerHelper::bitcast(MachineInstr &MI, unsigned TypeIdx, LLT CastTy) { function in class:LegalizerHelper
2883 dbgs() << "bitcast action not implemented for vector select\n");
3989 // FIXME: Can we do without the bitcast here if we're narrowing?
4054 // a final bitcast, otherwise use the original result register
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| LegalizerInfo.h | 72 Bitcast,
600 return actionIf(LegalizeAction::Bitcast, Predicate, Mutation);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64LegalizerInfo.cpp | 546 // etc. and in addition to this you can also bitcast with it at the same
939 // allow the existing patterns for s64 to fire for p0, we just try to bitcast
959 auto Bitcast = MIRBuilder.buildBitcast(NewTy, ValReg);
960 MIRBuilder.buildStore(Bitcast.getReg(0), MI.getOperand(1), MMO);
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| InstCombineCompares.cpp | 2777 auto *Bitcast = dyn_cast<BitCastInst>(Cmp.getOperand(0));
2778 if (!Bitcast)
2783 Value *BCSrcOp = Bitcast->getOperand(0);
2785 // Make sure the bitcast doesn't change the number of vector elements.
2786 if (Bitcast->getSrcTy()->getScalarSizeInBits() ==
2787 Bitcast->getDestTy()->getScalarSizeInBits()) {
2788 // Zero-equality and sign-bit checks are preserved through sitofp + bitcast.
2791 // icmp eq (bitcast (sitofp X)), 0 --> icmp eq X, 0
2792 // icmp ne (bitcast (sitofp X)), 0 --> icmp ne X, 0
2793 // icmp slt (bitcast (sitofp X)), 0 --> icmp slt X,
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Instrumentation/ |
| HWAddressSanitizer.cpp | 1308 auto *Bitcast = new BitCastInst(NewAI, AI->getType(), "", AI);
1309 AI->replaceAllUsesWith(Bitcast);
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 897 /// Return true if this instruction is a bitcast instruction.
899 return hasProperty(MCID::Bitcast, Type);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 1657 // Bitcast vector to appropriate type to ensure ISel pattern coverage
2061 // (shuffle (vNxT1 (bitcast (vNxT0 x))), undef, mask) ->
2062 // (vNxT1 (bitcast (vNxT0 (shuffle x, undef, mask))))
2063 SDValue Bitcast = N->getOperand(0);
2064 if (Bitcast.getOpcode() != ISD::BITCAST)
2068 SDValue CastOp = Bitcast.getOperand(0);
2070 MVT DstType = Bitcast.getSimpleValueType();
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 1372 // With bitcast'd call targets, the instruction will be the call
1379 // Ignore any bitcast instructions
1384 // Look through the bitcast
1914 return DAG.getNode(ISD::BITCAST, SDLoc(Op), MVT::v2f16, Const);
2088 SDValue Bitcast = DAG.getNode(ISD::BITCAST, SL, MVT::i32, A);
2090 SDValue Sign = DAG.getNode(ISD::AND, SL, MVT::i32, Bitcast,
2097 DAG.getNode(ISD::BITCAST, SL, VT, PointFiveWithSignRaw);
2564 // using i32 here and then bitcast back.
2586 // v2f16 was loaded as an i32. Now we must bitcast it back
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 504 setOperationAction(ISD::BITCAST, MVT::f32, Legal);
505 setOperationAction(ISD::BITCAST, MVT::i32, Legal);
506 setOperationAction(ISD::BITCAST, MVT::i64, Legal);
507 setOperationAction(ISD::BITCAST, MVT::f64, Legal);
519 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
520 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
521 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
522 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
1174 setOperationAction(ISD::BITCAST, MVT::i128, Custom);
2646 // %b = bitcast i1* %a to i64
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 243 setOperationAction(ISD::BITCAST, VT, Legal);
389 // We 'support' these types up to bitcast/load/store level, regardless of
752 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
753 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
763 setOperationAction(ISD::BITCAST, MVT::bf16, Custom);
993 setTargetDAGCombine(ISD::BITCAST);
1345 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
2064 Val = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocVT.getSizeInBits()),
2071 Val = DAG.getNode(ISD::BITCAST, dl, ValVT, Val);
2083 Val = DAG.getNode(ISD::BITCAST, dl
[all...] |
