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    Searched refs:Br (Results 1 - 25 of 62) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsBranchExpansion.cpp 129 MachineInstr *Br = nullptr;
156 int64_t computeOffset(const MachineInstr *Br);
158 void replaceBranch(MachineBasicBlock &MBB, Iter Br, const DebugLoc &DL,
223 /// Iterate over list of Br's operands and search for a MachineBasicBlock
225 static MachineBasicBlock *getTargetMBB(const MachineInstr &Br) {
226 for (unsigned I = 0, E = Br.getDesc().getNumOperands(); I < E; ++I) {
227 const MachineOperand &MO = Br.getOperand(I);
304 int64_t MipsBranchExpansion::computeOffset(const MachineInstr *Br) {
306 int ThisMBB = Br->getParent()->getNumber();
307 int TargetMBB = getTargetMBB(*Br)->getNumber()
    [all...]
MipsConstantIslandPass.cpp 405 bool fixupImmediateBr(ImmBranch &Br);
406 bool fixupConditionalBr(ImmBranch &Br);
407 bool fixupUnconditionalBr(ImmBranch &Br);
501 LLVM_DEBUG(dbgs() << "Beginning BR iteration #" << NoBRIters << '\n');
1478 bool MipsConstantIslands::fixupImmediateBr(ImmBranch &Br) {
1479 MachineInstr *MI = Br.MI;
1484 if (isBBInRange(MI, DestBB, Br.MaxDisp))
1487 if (!Br.isCond)
1488 return fixupUnconditionalBr(Br);
1489 return fixupConditionalBr(Br);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCPreEmitPeephole.cpp 483 MachineInstr *Br = &*I;
484 if (Br->getOpcode() != PPC::BC && Br->getOpcode() != PPC::BCn)
487 Register CRBit = Br->getOperand(0).getReg();
490 MachineBasicBlock::reverse_iterator It = Br, Er = MBB.rend();
505 if ((Br->getOpcode() == PPC::BCn && CRSetOp == PPC::CRSET) ||
506 (Br->getOpcode() == PPC::BC && CRSetOp == PPC::CRUNSET)) {
508 InstrsToErase.push_back(Br);
509 MBB.removeSuccessor(Br->getOperand(1).getMBB());
514 MachineBasicBlock::iterator It = Br, Er = MBB.end()
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMConstantIslandPass.cpp 266 bool fixupImmediateBr(ImmBranch &Br);
267 bool fixupConditionalBr(ImmBranch &Br);
268 bool fixupUnconditionalBr(ImmBranch &Br);
457 LLVM_DEBUG(dbgs() << "Beginning BR iteration #" << NoBRIters << '\n');
1646 bool ARMConstantIslands::fixupImmediateBr(ImmBranch &Br) {
1647 MachineInstr *MI = Br.MI;
1651 if (BBUtils->isBBInRange(MI, DestBB, Br.MaxDisp))
1654 if (!Br.isCond)
1655 return fixupUnconditionalBr(Br);
1656 return fixupConditionalBr(Br);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/
VPlanHCFGBuilder.cpp 205 if (auto *Br = dyn_cast<BranchInst>(Inst)) {
208 if (Br->isConditional())
209 getOrCreateVPOperand(Br->getCondition());
298 auto *Br = cast<BranchInst>(TI);
299 Value *BrCond = Br->getCondition();
LoopVectorizationLegality.cpp 435 auto *Br = dyn_cast<BranchInst>(BB->getTerminator());
436 if (!Br) {
452 if (!EnableVPlanPredication && Br && Br->isConditional() &&
453 !TheLoop->isLoopInvariant(Br->getCondition()) &&
454 !LI->isLoopHeader(Br->getSuccessor(0)) &&
455 !LI->isLoopHeader(Br->getSuccessor(1))) {
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
ConstraintElimination.cpp 271 auto *Br = dyn_cast<BranchInst>(BB.getTerminator());
272 if (!Br || !Br->isConditional())
288 if (match(Br->getCondition(), m_LogicalOr(m_Value(Op0), m_Value(Op1))) &&
290 BasicBlock *FalseSuccessor = Br->getSuccessor(1);
303 if (match(Br->getCondition(), m_LogicalAnd(m_Value(Op0), m_Value(Op1))) &&
305 BasicBlock *TrueSuccessor = Br->getSuccessor(0);
315 auto *CmpI = dyn_cast<CmpInst>(Br->getCondition());
318 if (CanAdd(Br->getSuccessor(0)))
319 WorkList.emplace_back(DT.getNode(Br->getSuccessor(0)), CmpI, false)
    [all...]
StructurizeCFG.cpp 959 auto Br = dyn_cast<BranchInst>(E->getEntry()->getTerminator());
960 if (!Br || !Br->isConditional())
963 if (!DA.isUniform(Br))
969 LLVM_DEBUG(dbgs() << "BB: " << Br->getParent()->getName()
982 auto Br = dyn_cast<BranchInst>(BB->getTerminator());
983 if (!Br || !Br->isConditional())
986 if (!Br->getMetadata(UniformMDKindID)) {
LoopFlatten.cpp 307 BranchInst *Br = dyn_cast<BranchInst>(&I);
308 if (Br && Br->isUnconditional() &&
309 Br->getSuccessor(0) == FI.InnerLoop->getHeader())
  /src/external/apache2/llvm/dist/clang/lib/CodeGen/
CGCleanup.cpp 368 if (llvm::BranchInst *Br = dyn_cast<llvm::BranchInst>(Term)) {
369 assert(Br->isUnconditional());
373 llvm::SwitchInst::Create(Load, Br->getSuccessor(0), 4, Block);
374 Br->eraseFromParent();
529 llvm::BranchInst *Br = dyn_cast<llvm::BranchInst>(Pred->getTerminator());
530 if (!Br || Br->isConditional()) return Entry;
531 assert(Br->getSuccessor(0) == Entry);
540 Br->eraseFromParent();
590 if (llvm::BranchInst *Br = dyn_cast<llvm::BranchInst>(Term))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUTargetTransformInfo.cpp 154 if (const BranchInst *Br = dyn_cast<BranchInst>(&I)) {
155 if (UP.Threshold < MaxBoost && Br->isConditional()) {
156 BasicBlock *Succ0 = Br->getSuccessor(0);
157 BasicBlock *Succ1 = Br->getSuccessor(1);
161 if (dependsOnLocalPhi(L, Br->getCondition())) {
165 << *L << " due to " << *Br << '\n');
822 case Instruction::Br: {
1326 case Instruction::Br:
AMDGPULegalizerInfo.cpp 2679 verifyCFIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineInstr *&Br,
2703 // Make sure the cond br is followed by a G_BR, or is the last instruction.
2713 Br = &*Next;
2714 UncondBrTarget = Br->getOperand(0).getMBB();
4690 MachineInstr *Br = nullptr;
4694 verifyCFIntrinsic(MI, MRI, Br, UncondBrTarget, Negated)) {
4719 if (Br) {
4720 Br->getOperand(0).setMBB(CondBrTarget);
4738 MachineInstr *Br = nullptr;
4742 verifyCFIntrinsic(MI, MRI, Br, UncondBrTarget, Negated))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
MSP430InstrInfo.cpp 119 I->getOpcode() != MSP430::Br &&
187 if (I->getOpcode() == MSP430::Br ||
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyFastISel.cpp 1301 const auto *Br = cast<BranchInst>(I);
1302 if (Br->isUnconditional()) {
1303 MachineBasicBlock *MSucc = FuncInfo.MBBMap[Br->getSuccessor(0)];
1304 fastEmitBranch(MSucc, Br->getDebugLoc());
1308 MachineBasicBlock *TBB = FuncInfo.MBBMap[Br->getSuccessor(0)];
1309 MachineBasicBlock *FBB = FuncInfo.MBBMap[Br->getSuccessor(1)];
1312 unsigned CondReg = getRegForI1Value(Br->getCondition(), Not);
1324 finishCondBranch(Br->getParent(), TBB, FBB);
1416 case Instruction::Br:
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86SpeculativeLoadHardening.cpp 226 MachineInstr *Br, MachineInstr *&UncondBr,
240 if (Br) {
241 assert(Br->getOperand(0).getMBB() == &Succ &&
243 Br->getOperand(0).setMBB(&NewMBB);
264 TII.insertBranch(NewMBB, &Succ, nullptr, Cond, Br->getDebugLoc());
727 MachineInstr *Br, MachineInstr *&UncondBr,
734 : splitEdge(MBB, Succ, SuccCount, Br, UncondBr, *TII);
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
InlineFunction.cpp 2522 Instruction *Br = OrigBB->getTerminator();
2523 assert(Br && Br->getOpcode() == Instruction::Br &&
2525 Br->setOperand(0, &*FirstNewBlock);
2617 assert(cast<BranchInst>(Br)->isUnconditional() && "splitBasicBlock broken!");
2618 BasicBlock *CalleeEntry = cast<BranchInst>(Br)->getSuccessor(0);
2623 OrigBB->getInstList().splice(Br->getIterator(), CalleeEntry->getInstList());
2626 OrigBB->getInstList().erase(Br);
BreakCriticalEdges.cpp 328 // terminator (that is, not a switch or a br).
339 case Instruction::Br:
  /src/external/apache2/llvm/dist/llvm/include/llvm/Transforms/InstCombine/
InstCombiner.h 283 case Instruction::Br:
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/AsmParser/
WebAssemblyAsmParser.cpp 149 for (auto Br : BrL.List)
150 Inst.addOperand(MCOperand::createImm(Br));
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
ObjCARCInstKind.cpp 247 case Instruction::Br:
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/IPO/
LowerTypeTests.cpp 786 // br(llvm.type.test(...), thenbb, elsebb)
787 // where nothing happens between the type test and the br.
790 if (auto *Br = dyn_cast<BranchInst>(*CI->user_begin()))
791 if (CI->getNextNode() == Br) {
793 BasicBlock *Else = Br->getSuccessor(1);
796 Br->getMetadata(LLVMContext::MD_prof));
  /src/external/apache2/llvm/dist/llvm/lib/Frontend/OpenMP/
OMPIRBuilder.cpp 1468 auto *Br = cast<BranchInst>(Term);
1469 Br->setSuccessor(0, OuterCond);
1504 auto *Br = cast<BranchInst>(Term);
1505 assert(!Br->isConditional() &&
1507 BasicBlock *Succ = Br->getSuccessor(0);
1509 Br->setSuccessor(0, Target);
  /src/external/apache2/llvm/dist/llvm/bindings/ocaml/llvm/
llvm.ml 182 | Br
1111 | Instruction (Br | IndirectBr | Invoke | Resume | Ret | Switch | Unreachable)
1155 if classify_value llv <> ValueKind.Instruction Opcode.Br then
  /src/crypto/external/apache2/openssl/dist/test/recipes/30-test_evp_data/
evppkey_ffdhe.txt 531 Risp2sTjgPCg1ox61zX+lD3JHvopO46qCvYHsCEgK80R3KY6MOBkdDn6XE5pN+Br
  /src/crypto/external/bsd/openssl/dist/test/recipes/30-test_evp_data/
evppkey_ffdhe.txt 531 Risp2sTjgPCg1ox61zX+lD3JHvopO46qCvYHsCEgK80R3KY6MOBkdDn6XE5pN+Br

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