| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86LoadValueInjectionRetHardening.cpp | 84 BuildMI(MBB, MBBI, DebugLoc(), TII->get(X86::POP64r))
87 BuildMI(MBB, MBBI, DebugLoc(), TII->get(X86::LFENCE));
88 BuildMI(MBB, MBBI, DebugLoc(), TII->get(X86::JMP64r))
97 BuildMI(MBB, MBBI, DebugLoc(), TII->get(X86::LFENCE));
98 addRegOffset(BuildMI(MBB, Fence, DebugLoc(), TII->get(X86::SHL64mi)),
|
| X86LowerTileCopy.cpp | 106 BuildMI(MBB, MI, DL, TII->get(X86::IMPLICIT_DEF), GR64Cand);
107 addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::MOV64mr)), StrideSS)
110 BuildMI(MBB, MI, DL, TII->get(X86::MOV64ri), GR64Cand).addImm(64);
114 addFrameReference(BuildMI(MBB, MI, DL, TII->get(Opc)), TileSS)
121 NewMI = addFrameReference(BuildMI(MBB, MI, DL, TII->get(Opc), DstReg),
125 addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::MOV64rm), GR64Cand),
|
| X86FrameLowering.cpp | 227 BuildMI(MBB, MBBI, DL, TII.get(X86::STACKALLOC_W_PROBING)).addImm(Offset);
244 BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Reg)
247 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AddSubRROpc), StackPtr)
261 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
270 BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Rax)
273 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(X86::ADD64rr), Rax)
279 BuildMI(MBB, MBBI, DL, TII.get(X86::XCHG64rm), Rax).addReg(Rax),
282 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), StackPtr),
300 BuildMI(MBB, MBBI, DL, TII.get(Opc))
346 MI = addRegOffset(BuildMI(MBB, MBBI, DL
[all...] |
| X86IndirectThunks.cpp | 95 BuildMI(&MF.front(), DebugLoc(), TII->get(X86::LFENCE));
96 BuildMI(&MF.front(), DebugLoc(), TII->get(X86::JMP64r)).addReg(X86::R11);
218 BuildMI(Entry, DebugLoc(), TII->get(CallOpc)).addSym(TargetSym);
233 BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::PAUSE));
234 BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::LFENCE));
235 BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::JMP_1)).addMBB(CaptureSpec);
246 addRegOffset(BuildMI(CallTarget, DebugLoc(), TII->get(MovOpc)), SPReg, false,
251 BuildMI(CallTarget, DebugLoc(), TII->get(RetOpc));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEFrameLowering.cpp | 152 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
157 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
164 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
169 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
176 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii))
200 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX17)
205 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX16)
209 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX15)
215 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX10)
219 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX9
[all...] |
| VEInstrInfo.cpp | 238 BuildMI(&MBB, DL, get(VE::BRCFLa_t))
270 BuildMI(&MBB, DL, get(opc[0]))
276 BuildMI(&MBB, DL, get(opc[1]))
286 BuildMI(&MBB, DL, get(VE::BRCFLa_t))
342 BuildMI(MBB, I, DL, MCID, SubDest).addReg(SubSrc).addImm(0);
347 BuildMI(MBB, I, DL, MCID, SubDest).addReg(VE::VM0).addReg(SubSrc);
365 BuildMI(MBB, I, DL, get(VE::ORri), DestReg)
378 BuildMI(MBB, I, DL, get(VE::LEAzii), TmpReg)
382 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(VE::VORmvl), DestReg)
388 BuildMI(MBB, I, DL, get(VE::ANDMmm), DestReg
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFInstrInfo.cpp | 36 BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg)
39 BuildMI(MBB, I, DL, get(BPF::MOV_rr_32), DestReg)
78 BuildMI(*BB, MI, dl, get(LdOpc))
81 BuildMI(*BB, MI, dl, get(StOpc))
92 BuildMI(*BB, MI, dl, get(BPF::LDW))
94 BuildMI(*BB, MI, dl, get(BPF::STW))
99 BuildMI(*BB, MI, dl, get(BPF::LDH))
101 BuildMI(*BB, MI, dl, get(BPF::STH))
106 BuildMI(*BB, MI, dl, get(BPF::LDB))
108 BuildMI(*BB, MI, dl, get(BPF::STB)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsExpandPseudo.cpp | 145 BuildMI(loop1MBB, DL, TII->get(LL), Scratch).addReg(Ptr).addImm(0);
146 BuildMI(loop1MBB, DL, TII->get(Mips::AND), Scratch2)
149 BuildMI(loop1MBB, DL, TII->get(BNE))
157 BuildMI(loop2MBB, DL, TII->get(Mips::AND), Scratch)
160 BuildMI(loop2MBB, DL, TII->get(Mips::OR), Scratch)
163 BuildMI(loop2MBB, DL, TII->get(SC), Scratch)
167 BuildMI(loop2MBB, DL, TII->get(BEQ))
175 BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest)
179 BuildMI(sinkMBB, DL, TII->get(SEOp), Dest).addReg(Dest);
183 BuildMI(sinkMBB, DL, TII->get(Mips::SLL), Dest
[all...] |
| MipsBranchExpansion.cpp | 340 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc);
396 BuildMI(*MBB, Pos, DL, TII->get(JumpOp)).addReg(ATReg);
465 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
468 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW))
489 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
494 BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB);
496 BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
511 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
514 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
526 BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::ADDiu), Mips::SP
[all...] |
| MipsMachineFunction.cpp | 87 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
89 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
91 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
101 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
103 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
116 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
118 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
119 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
145 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 9 // This file exposes a function named BuildMI, which is useful for dramatically
12 // M = BuildMI(MBB, MI, DL, TII.get(X86::ADD8rr), Dst)
328 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
335 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
344 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
360 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
370 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
376 return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID, DestReg);
377 return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID, DestReg);
380 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiFrameLowering.cpp | 78 BuildMI(*MBB, MI, DL, LII.get(Lanai::ADD_I_LO), Dst)
113 BuildMI(MBB, MBBI, DL, LII.get(Lanai::SW_RI))
122 BuildMI(MBB, MBBI, DL, LII.get(Lanai::ADD_I_LO), Lanai::FP)
130 BuildMI(MBB, MBBI, DL, LII.get(Lanai::SUB_I_LO), Lanai::SP)
186 BuildMI(MBB, MBBI, DL, LII.get(Lanai::ADD_I_LO), Lanai::SP)
191 BuildMI(MBB, MBBI, DL, LII.get(Lanai::LDW_RI), Lanai::FP)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 255 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
263 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
265 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
269 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
322 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
330 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
334 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
345 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)
361 BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg)
366 BuildMI(MBB, I, DL, get(SP::RDASR), DestReg
[all...] |
| SparcFrameLowering.cpp | 52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
81 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
156 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
161 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
169 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::R4)
98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP)
135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::R4);
156 BuildMI(MBB, MBBI, DL,
160 BuildMI(MBB, MBBI, DL,
170 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SP)
197 BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r))
216 BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg());
242 BuildMI(MF, Old.getDebugLoc(), TII.get(MSP430::SUB16ri), MSP430::SP
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| FEntryInserter.cpp | 45 BuildMI(FirstMBB, FirstMBB.begin(), DebugLoc(),
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCTLSDynamicCall.cpp | 139 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0)
150 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR4)
152 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR3)
154 BuildMI(MBB, I, DL, TII->get(Opc2), GPR3).addReg(GPR3).addReg(GPR4);
158 Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addImm(0);
162 Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addReg(InReg);
168 (BuildMI(MBB, I, DL, TII->get(Opc2), GPR3).addReg(GPR3));
175 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKUP)).addImm(0).addImm(0);
177 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), OutReg)
|
| PPCFrameLowering.cpp | 796 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFOCRF8), TempReg);
800 BuildMI(MBB, MBBI, dl, MoveFromCondRegInst, TempReg);
810 BuildMI(MBB, MBBI, dl, StoreWordInst)
817 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
824 BuildMI(MBB, MBBI, dl, StoreInst)
829 BuildMI(MBB, MBBI, dl, StoreInst)
834 BuildMI(MBB, MBBI, dl, StoreInst)
844 BuildMI(MBB, StackUpdateLoc, dl, StoreInst)
862 BuildMI(MBB, StackUpdateLoc, dl, HashST)
872 BuildMI(MBB, MBBI, dl, StoreWordInst
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVExpandAtomicPseudoInsts.cpp | 233 BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg)
239 BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg)
242 BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg)
247 BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg)
250 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE))
267 BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg)
270 BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg)
273 BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg)
299 BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg)
305 BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRFrameLowering.cpp | 63 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs))
71 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr))
75 BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), AVR::R0)
78 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr))
81 BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr))
104 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPREAD), AVR::R29R28)
121 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28)
129 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP)
146 BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), AVR::R0);
147 BuildMI(MBB, MBBI, DL, TII.get(AVR::OUTARr)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCFrameLowering.cpp | 72 BuildMI(MBB, MBBI, dl, TII.get(AdjOp), StackPtr)
142 BuildMI(MBB, MBBI, dl, TII->get(Opc), ARC::SP)
148 BuildMI(MBB, MBBI, dl, TII->get(ARC::ST_AW_rs9))
159 BuildMI(MBB, MBBI, dl, TII->get(ARC::PUSH_S_BLINK));
160 BuildMI(MBB, MBBI, dl, TII->get(ARC::SUB_rru6))
164 BuildMI(MBB, MBBI, dl, TII->get(ARC::BL))
173 BuildMI(MBB, MBBI, dl, TII->get(ARC::PUSH_S_BLINK));
186 BuildMI(MBB, MBBI, dl,
200 BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION))
208 BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ExpandPseudoInsts.cpp | 147 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
157 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
168 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
215 BuildMI(LoadCmpBB, DL, TII->get(AArch64::MOVZWi), StatusReg)
217 BuildMI(LoadCmpBB, DL, TII->get(LdarOp), Dest.getReg())
219 BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg)
223 BuildMI(LoadCmpBB, DL, TII->get(AArch64::Bcc))
233 BuildMI(StoreBB, DL, TII->get(StlrOp), StatusReg)
236 BuildMI(StoreBB, DL, TII->get(AArch64::CBNZW))
296 BuildMI(LoadCmpBB, DL, TII->get(AArch64::LDAXPX)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyFrameLowering.cpp | 185 BuildMI(MBB, InsertStore, DL, TII->get(getOpcGlobSet(MF)))
235 BuildMI(MBB, InsertPt, DL, TII->get(getOpcGlobGet(MF)), SPReg)
243 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::COPY), BasePtr)
249 BuildMI(MBB, InsertPt, DL, TII->get(getOpcConst(MF)), OffsetReg)
251 BuildMI(MBB, InsertPt, DL, TII->get(getOpcSub(MF)), getSPReg(MF))
258 BuildMI(MBB, InsertPt, DL, TII->get(getOpcConst(MF)), BitmaskReg)
260 BuildMI(MBB, InsertPt, DL, TII->get(getOpcAnd(MF)), getSPReg(MF))
268 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::COPY), getFPReg(MF))
301 BuildMI(MBB, InsertPt, DL, TII->get(getOpcConst(MF)), OffsetReg)
307 BuildMI(MBB, InsertPt, DL, TII->get(getOpcAdd(MF)), SPReg
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 336 BuildMI(MBB, std::next(Info.I), dl,
377 BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg)
382 BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg)
392 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
397 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
407 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg)
611 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
616 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4)
626 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
633 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 70 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
76 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
83 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
106 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
112 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
119 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
140 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
146 BuildMI(MBB, II, dl, TII.get(NewOpcode))
153 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
176 BuildMI(MBB, II, dl, TII.get(XCore::LDAWSP_ru6), ScratchBase).addImm(0)
[all...] |
