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    Searched refs:CACHELINE_SIZE (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/arch/arm/arm/
cpufunc_asm_fa526.S 35 #define CACHELINE_SIZE 16
124 and r2, r0, #(CACHELINE_SIZE-1)
126 bic r0, r0, #(CACHELINE_SIZE-1)
129 add r0, r0, #CACHELINE_SIZE
130 subs r1, r1, #CACHELINE_SIZE
145 1: and r2, r0, #(CACHELINE_SIZE-1)
147 bic r0, r0, #(CACHELINE_SIZE-1)
150 add r0, r0, #CACHELINE_SIZE
151 subs r1, r1, #CACHELINE_SIZE
159 and r2, r0, #(CACHELINE_SIZE-1
    [all...]
  /src/sys/arch/m68k/m68k/
bus_dma.c 523 while ((p < e) && (p & (CACHELINE_SIZE * 8 - 1)) != 0) {
525 p += CACHELINE_SIZE;
529 while ((p + CACHELINE_SIZE * 8 <= e) &&
532 p += CACHELINE_SIZE;
534 p += CACHELINE_SIZE;
536 p += CACHELINE_SIZE;
538 p += CACHELINE_SIZE;
540 p += CACHELINE_SIZE;
542 p += CACHELINE_SIZE;
544 p += CACHELINE_SIZE;
    [all...]
  /src/sys/arch/atari/atari/
bus.c 658 while ((p < e) && (p & (CACHELINE_SIZE * 8 - 1)) != 0) {
660 p += CACHELINE_SIZE;
666 p += CACHELINE_SIZE;
668 p += CACHELINE_SIZE;
670 p += CACHELINE_SIZE;
672 p += CACHELINE_SIZE;
674 p += CACHELINE_SIZE;
676 p += CACHELINE_SIZE;
678 p += CACHELINE_SIZE;
680 p += CACHELINE_SIZE;
    [all...]
  /src/sys/arch/m68k/include/
cpu.h 129 #define CACHELINE_SIZE 16
130 #define CACHELINE_MASK (CACHELINE_SIZE - 1)
  /src/external/bsd/zstd/dist/lib/common/
compiler.h 156 #define CACHELINE_SIZE 64
163 for (_pos=0; _pos<_size; _pos+=CACHELINE_SIZE) { \
  /src/sys/arch/amiga/pci/
mppb.c 174 pci_configure_bus(pc, pcires, 0, CACHELINE_SIZE);
em4k.c 258 pci_configure_bus(&sc->apc, pcires, 0, CACHELINE_SIZE);
empb.c 238 pci_configure_bus(pc, pcires, 0, CACHELINE_SIZE);
p5pb.c 504 pci_configure_bus(pc, pcires, 0, CACHELINE_SIZE);
  /src/external/bsd/zstd/dist/lib/decompress/
zstd_decompress_block.c 1723 PREFETCH_L1(match); PREFETCH_L1(match+CACHELINE_SIZE); /* note : it's safe to invoke PREFETCH() on any memory address, including invalid ones */

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