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    Searched refs:CACHE_R4K_D (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/arch/cobalt/stand/boot/
start.S 82 cache CACHE_R4K_D | CACHEOP_R4K_INDEX_WB_INV, 0x000(t0)
83 cache CACHE_R4K_D | CACHEOP_R4K_INDEX_WB_INV, 0x020(t0)
84 cache CACHE_R4K_D | CACHEOP_R4K_INDEX_WB_INV, 0x040(t0)
85 cache CACHE_R4K_D | CACHEOP_R4K_INDEX_WB_INV, 0x060(t0)
86 cache CACHE_R4K_D | CACHEOP_R4K_INDEX_WB_INV, 0x080(t0)
87 cache CACHE_R4K_D | CACHEOP_R4K_INDEX_WB_INV, 0x0a0(t0)
88 cache CACHE_R4K_D | CACHEOP_R4K_INDEX_WB_INV, 0x0c0(t0)
89 cache CACHE_R4K_D | CACHEOP_R4K_INDEX_WB_INV, 0x0e0(t0)
cache.c 60 cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
74 cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
88 cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
  /src/sys/arch/mips/mips/
cache_r5k.c 236 cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
256 cache_r4k_op_32lines_32(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
261 cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
276 cache_r4k_op_32lines_16(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
277 cache_r4k_op_32lines_16(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
282 cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
283 cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
306 cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
330 cache_r4k_op_32lines_32(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
336 cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV)
    [all...]
cache_r10k.c 166 cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
168 cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
181 cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
204 cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
206 cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
219 cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
233 cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
cache_r4k_subr.S 205 emitops OPNAME32(pdcache_index_wb_inv), CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV
206 emitops OPNAME32(pdcache_hit_inv), CACHE_R4K_D|CACHEOP_R4K_HIT_INV
207 emitops OPNAME32(pdcache_hit_wb_inv), CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV
208 emitops OPNAME32(pdcache_hit_wb), CACHE_R4K_D|CACHEOP_R4K_HIT_WB
mipsX_subr.S 2904 cache (CACHE_R4K_D | CACHEOP_R4K_HIT_INV), 0(k0)
  /src/sys/arch/evbmips/ingenic/
cpu_startup.S 107 cache CACHEOP_R4K_INDEX_STORE_TAG | CACHE_R4K_D, 0(t0)
  /src/sys/arch/mips/include/
cache_r4k.h 43 #define CACHE_R4K_D 1

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