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    Searched refs:CC_C0S (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/mips/alchemy/dev/
aurtc.c	160 while (GETREG(PC_COUNTER_CONTROL) & CC_C0S) { 180 while (GETREG(PC_COUNTER_CONTROL) & CC_C0S) {
/src/sys/arch/mips/alchemy/include/
aureg.h	251 #define CC_C0S 0x00000001 /* PC0 write status */

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