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    Searched refs:CC_SW_RST1 (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/mips/ingenic/
ingenic_coreregs.h	41 #define CC_SW_RST1 __BIT(1) /* reset core 1 */
/src/sys/arch/evbmips/ingenic/
cpu.c	96 reg &= ~CC_SW_RST1; /* get core 1 out of reset */

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