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    Searched refs:CC_T1S (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/mips/alchemy/
au_timer.c	84 SET_PC_REG(PC_TRIM1, CC_T1S, PC_RATE / 16 - 1);
/src/sys/arch/mips/alchemy/include/
aureg.h	234 #define CC_T1S 0x00100000 /* Trim PC1 write status */

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