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    Searched refs:CGC_CLK_GATE_DLY_TIMER (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_vce_v2_0.c	141 tmp |= (CGC_CLK_GATE_DLY_TIMER(0) | CGC_CLK_GATER_OFF_DLY_TIMER(4));
cikd.h	2123 # define CGC_CLK_GATE_DLY_TIMER(x) ((x) << 0)

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