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Searched refs:CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK (Results 1 - 9 of 9) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_ci_baco.c	`100 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK, CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT, 0, 0x1 },`
amdgpu_fiji_baco.c	`89 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK, CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT, 0, 0x1 },`
amdgpu_tonga_baco.c	`91 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK, CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT, 0, 0x1 },`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_7_0_0_sh_mask.h	`103 #define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1`
smu_7_1_1_sh_mask.h	`103 #define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1`
smu_7_0_1_sh_mask.h	`103 #define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1`
smu_7_1_0_sh_mask.h	`103 #define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1`
smu_7_1_2_sh_mask.h	`103 #define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1`
smu_7_1_3_sh_mask.h	`127 #define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1`

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