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Searched
refs:CG_UPLL_FUNC_CNTL
(Results
1 - 9
of
9
) sorted by relevancy
/src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_rv770.c
72
WREG32_P(
CG_UPLL_FUNC_CNTL
, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
90
WREG32_P(
CG_UPLL_FUNC_CNTL
, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK));
93
WREG32_P(
CG_UPLL_FUNC_CNTL
, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
96
r = radeon_uvd_send_upll_ctlreq(rdev,
CG_UPLL_FUNC_CNTL
);
101
WREG32_P(
CG_UPLL_FUNC_CNTL
, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
104
WREG32_P(
CG_UPLL_FUNC_CNTL
, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK);
119
WREG32_P(
CG_UPLL_FUNC_CNTL
, 0, ~UPLL_RESET_MASK);
124
WREG32_P(
CG_UPLL_FUNC_CNTL
, 0, ~UPLL_BYPASS_EN_MASK);
127
r = radeon_uvd_send_upll_ctlreq(rdev,
CG_UPLL_FUNC_CNTL
);
radeon_r600.c
221
WREG32_P(
CG_UPLL_FUNC_CNTL
, UPLL_BYPASS_EN_MASK, ~(
230
WREG32_P(
CG_UPLL_FUNC_CNTL
, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
250
r = radeon_uvd_send_upll_ctlreq(rdev,
CG_UPLL_FUNC_CNTL
);
255
WREG32_P(
CG_UPLL_FUNC_CNTL
, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
259
WREG32_P(
CG_UPLL_FUNC_CNTL
, UPLL_REFCLK_SRC_SEL_MASK,
263
WREG32_P(
CG_UPLL_FUNC_CNTL
,
279
WREG32_P(
CG_UPLL_FUNC_CNTL
, 0, ~UPLL_RESET_MASK);
284
WREG32_P(
CG_UPLL_FUNC_CNTL
, 0, ~UPLL_BYPASS_EN_MASK);
289
r = radeon_uvd_send_upll_ctlreq(rdev,
CG_UPLL_FUNC_CNTL
);
radeon_evergreen.c
1209
WREG32_P(
CG_UPLL_FUNC_CNTL
, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
1213
WREG32_P(
CG_UPLL_FUNC_CNTL
, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
1224
WREG32_P(
CG_UPLL_FUNC_CNTL
, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
1227
WREG32_P(
CG_UPLL_FUNC_CNTL
, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
1228
WREG32_P(
CG_UPLL_FUNC_CNTL
, 0, ~UPLL_SLEEP_MASK);
1231
WREG32_P(
CG_UPLL_FUNC_CNTL
, 0, ~UPLL_RESET_MASK);
1235
r = radeon_uvd_send_upll_ctlreq(rdev,
CG_UPLL_FUNC_CNTL
);
1240
WREG32_P(
CG_UPLL_FUNC_CNTL
, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
1249
WREG32_P(
CG_UPLL_FUNC_CNTL
, 0, ~UPLL_REF_DIV_MASK);
1265
WREG32_P(
CG_UPLL_FUNC_CNTL
, 0, ~UPLL_RESET_MASK)
[
all
...]
radeon_si.c
7022
WREG32_P(
CG_UPLL_FUNC_CNTL
, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
7039
WREG32_P(
CG_UPLL_FUNC_CNTL
, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
7042
WREG32_P(
CG_UPLL_FUNC_CNTL
, 0, ~UPLL_SLEEP_MASK);
7045
WREG32_P(
CG_UPLL_FUNC_CNTL
, 0, ~UPLL_RESET_MASK);
7049
r = radeon_uvd_send_upll_ctlreq(rdev,
CG_UPLL_FUNC_CNTL
);
7054
WREG32_P(
CG_UPLL_FUNC_CNTL
, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
7063
WREG32_P(
CG_UPLL_FUNC_CNTL
, 0, ~UPLL_REF_DIV_MASK);
7079
WREG32_P(
CG_UPLL_FUNC_CNTL
, 0, ~UPLL_RESET_MASK);
7084
WREG32_P(
CG_UPLL_FUNC_CNTL
, 0, ~UPLL_BYPASS_EN_MASK);
7086
r = radeon_uvd_send_upll_ctlreq(rdev,
CG_UPLL_FUNC_CNTL
);
[
all
...]
rv770d.h
44
#define
CG_UPLL_FUNC_CNTL
0x718
sid.h
129
#define
CG_UPLL_FUNC_CNTL
0x634
evergreend.h
350
#define
CG_UPLL_FUNC_CNTL
0x718
r600d.h
1558
#define
CG_UPLL_FUNC_CNTL
0x7e0
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
sid.h
131
#define
CG_UPLL_FUNC_CNTL
0x18d
Completed in 50 milliseconds
Indexes created Fri Oct 17 17:09:57 GMT 2025