| /src/sys/external/bsd/sljit/dist/sljit_src/ |
| sljitExecAllocator.c | 71 #define CHUNK_SIZE 0x10000
76 * the size is always divisible by CHUNK_SIZE
144 #define CHUNK_MASK (~(CHUNK_SIZE - 1))
199 sljit_uw chunk_size; local in function:sljit_malloc_exec
209 chunk_size = free_block->size;
210 if (chunk_size > size + 64) {
212 chunk_size -= size;
213 free_block->size = chunk_size;
214 header = AS_BLOCK_HEADER(free_block, chunk_size);
215 header->prev_size = chunk_size;
[all...] |
| sljitProtExecAllocator.c | 69 #define CHUNK_SIZE 0x10000
79 * the size is always divisible by CHUNK_SIZE
215 #define CHUNK_MASK (~(CHUNK_SIZE - 1))
272 sljit_uw chunk_size; local in function:sljit_malloc_exec
283 chunk_size = free_block->size;
284 if (chunk_size > size + 64) {
286 chunk_size -= size;
287 free_block->size = chunk_size;
288 header = AS_BLOCK_HEADER(free_block, chunk_size);
289 header->prev_size = chunk_size;
[all...] |
| /src/sys/arch/arm/arm32/ |
| bcopy_page.S | 63 #define CHUNK_SIZE 32
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| dcn10_hubp.h | 343 HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\
541 type CHUNK_SIZE;\
|
| amdgpu_dcn10_hubp.c | 559 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
568 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
1041 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
1051 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| dcn20_dsc.h | 145 DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CHUNK_SIZE, mask_sh), \
320 type CHUNK_SIZE; \
|
| amdgpu_dcn20_hubp.c | 211 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
220 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
1233 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
1243 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
1276 CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size,
1285 CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size,
1310 if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size
[all...] |
| amdgpu_dcn20_dsc.c | 598 CHUNK_SIZE, reg_vals->pps.slice_chunk_size);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_hubp.c | 141 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
150 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
377 CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size,
386 CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size,
410 if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size)
411 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n",
412 dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/include/ |
| navi10_enum.h | 1814 * CHUNK_SIZE enum
1817 typedef enum CHUNK_SIZE {
1825 } CHUNK_SIZE;
|
