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    Searched refs:CIU_INT_MBOX_15_0 (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/arch/mips/cavium/
octeon_intr.c 174 .ih_irq = CIU_INT_MBOX_15_0,
202 [CIU_INT_MBOX_15_0] = &ipi_intrhands[0],
280 cpu->cpu_ip4_enable[0] |= __BIT(CIU_INT_MBOX_15_0);
  /src/sys/arch/mips/cavium/dev/
octeon_ciureg.h 173 #define CIU_INT_MBOX_15_0 32

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