| /src/sys/arch/arm/nxp/ |
| imx6sx_clk.c | 1135 CLK_GATE("aips_tz1", "ahb", CCM, CCGR0, AIPS_TZ1_CLK_ENABLE),
1136 CLK_GATE("aips_tz2", "ahb", CCM, CCGR0, AIPS_TZ2_CLK_ENABLE),
1137 CLK_GATE("apbh_dma", "usdhc3", CCM, CCGR0, APBHDMA_HCLK_ENABLE),
1138 CLK_GATE("asrc_ipg", "ahb", CCM, CCGR0, ASRC_CLK_ENABLE),
1139 CLK_GATE("asrc_mem", "ahb", CCM, CCGR0, ASRC_CLK_ENABLE),
1140 CLK_GATE("caam_mem", "ahb", CCM, CCGR0, CAAM_SECURE_MEM_CLK_ENABLE),
1141 CLK_GATE("caam_aclk", "ahb", CCM, CCGR0, CAAM_WRAPPER_ACLK_ENABLE),
1142 CLK_GATE("caam_ipg", "ipg", CCM, CCGR0, CAAM_WRAPPER_IPG_ENABLE),
1143 CLK_GATE("can1_ipg", "ipg", CCM, CCGR0, CAN1_CLK_ENABLE),
1144 CLK_GATE("can1_serial", "can_podf", CCM, CCGR0, CAN1_SERIAL_CLK_ENABLE)
[all...] |
| imx6_clk.c | 1045 CLK_GATE("apbh_dma", "usdhc3", CCM, CCGR0, APBHDMA_HCLK_ENABLE),
1046 CLK_GATE("asrc", "asrc_podf", CCM, CCGR0, ASRC_CLK_ENABLE),
1047 CLK_GATE("asrc_ipg", "ahb", CCM, CCGR0, ASRC_CLK_ENABLE),
1048 CLK_GATE("asrc_mem", "ahb", CCM, CCGR0, ASRC_CLK_ENABLE),
1049 CLK_GATE("caam_mem", "ahb", CCM, CCGR0, CAAM_SECURE_MEM_CLK_ENABLE),
1050 CLK_GATE("caam_aclk", "ahb", CCM, CCGR0, CAAM_WRAPPER_ACLK_ENABLE),
1051 CLK_GATE("caam_ipg", "ipg", CCM, CCGR0, CAAM_WRAPPER_IPG_ENABLE),
1052 CLK_GATE("can1_ipg", "ipg", CCM, CCGR0, CAN1_CLK_ENABLE),
1053 CLK_GATE("can1_serial", "can_root", CCM, CCGR0, CAN1_SERIAL_CLK_ENABLE),
1054 CLK_GATE("can2_ipg", "ipg", CCM, CCGR0, CAN2_CLK_ENABLE)
[all...] |
| imx6_ccmvar.h | 287 #define CLK_GATE(_name, _parent, _base, _reg, _mask) { \
|
| /src/sys/arch/arm/samsung/ |
| exynos5410_clock.c | 182 #define CLK_GATE(_name, _parent, _reg, _bits, _f) { \
343 CLK_GATE("sss", "aclk266", EXYNOS5410_GATE_IP_G2D, __BIT(2), 0),
345 CLK_GATE("mct", "aclk66", EXYNOS5410_GATE_IP_PERIS, __BIT(18), 0),
346 CLK_GATE("wdt", "aclk66", EXYNOS5410_GATE_IP_PERIS, __BIT(19), 0),
347 CLK_GATE("rtc", "aclk66", EXYNOS5410_GATE_IP_PERIS, __BIT(20), 0),
348 CLK_GATE("tmu", "aclk66", EXYNOS5410_GATE_IP_PERIS, __BIT(21), 0),
350 CLK_GATE("sclk_mmc0", "dout_mmc_pre0", EXYNOS5410_SRC_MASK_FSYS,
352 CLK_GATE("sclk_mmc1", "dout_mmc_pre1", EXYNOS5410_SRC_MASK_FSYS,
354 CLK_GATE("sclk_mmc2", "dout_mmc_pre2", EXYNOS5410_SRC_MASK_FSYS,
357 CLK_GATE("mmc0", "aclk200", EXYNOS5410_GATE_BUS_FSYS0, __BIT(12), 0)
[all...] |
| exynos5422_clock.c | 322 #define CLK_GATE(_name, _parent, _reg, _bits, _f) { \
517 CLK_GATE("aclk200_fsys", "mout_user_aclk200_fsys", EXYNOS5422_GATE_BUS_FSYS0,
519 CLK_GATE("aclk200_fsys2", "mout_user_aclk200_fsys2", EXYNOS5422_GATE_BUS_FSYS0,
522 CLK_GATE("sclk_mmc0", "dout_mmc0", EXYNOS5422_GATE_TOP_SCLK_FSYS,
524 CLK_GATE("sclk_mmc1", "dout_mmc1", EXYNOS5422_GATE_TOP_SCLK_FSYS,
526 CLK_GATE("sclk_mmc2", "dout_mmc2", EXYNOS5422_GATE_TOP_SCLK_FSYS,
528 CLK_GATE("sclk_usbphy301", "dout_usbphy301", EXYNOS5422_GATE_TOP_SCLK_FSYS,
530 CLK_GATE("sclk_usbphy300", "dout_usbphy300", EXYNOS5422_GATE_TOP_SCLK_FSYS,
532 CLK_GATE("sclk_usbd300", "dout_usbd300", EXYNOS5422_GATE_TOP_SCLK_FSYS,
534 CLK_GATE("sclk_usbd301", "dout_usbd301", EXYNOS5422_GATE_TOP_SCLK_FSYS
[all...] |
| /src/sys/arch/arm/nvidia/ |
| tegra210_car.c | 355 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \
369 CLK_GATE(_name, _parent, \
374 CLK_GATE(_name, _parent, \
379 CLK_GATE(_name, _parent, \
384 CLK_GATE(_name, _parent, \
389 CLK_GATE(_name, _parent, \
394 CLK_GATE(_name, _parent, \
399 CLK_GATE(_name, _parent, \
405 CLK_GATE(_name, _parent, _reg, _reg, _bits)
|
| tegra124_car.c | 343 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \
357 CLK_GATE(_name, _parent, \
362 CLK_GATE(_name, _parent, \
367 CLK_GATE(_name, _parent, \
372 CLK_GATE(_name, _parent, \
377 CLK_GATE(_name, _parent, \
382 CLK_GATE(_name, _parent, \
387 CLK_GATE(_name, _parent, _reg, _reg, _bits)
|
