| /src/sys/dev/clk/ |
| clk_backend.h | 47 #define CLK_SET_RATE_PARENT 0x01
|
| clk.c | 234 if (clk->flags & CLK_SET_RATE_PARENT)
|
| /src/sys/arch/arm/samsung/ |
| exynos5422_clock.c | 454 CLK_SET_RATE_PARENT, mout_epll_p),
456 CLK_SET_RATE_PARENT, mout_rpll_p),
518 __BIT(9), CLK_SET_RATE_PARENT),
520 __BIT(10), CLK_SET_RATE_PARENT),
523 __BIT(0), CLK_SET_RATE_PARENT),
525 __BIT(1), CLK_SET_RATE_PARENT),
527 __BIT(2), CLK_SET_RATE_PARENT),
529 __BIT(7), CLK_SET_RATE_PARENT),
531 __BIT(8), CLK_SET_RATE_PARENT),
533 __BIT(9), CLK_SET_RATE_PARENT),
[all...] |
| exynos5410_clock.c | 326 CLK_SET_RATE_PARENT),
328 CLK_SET_RATE_PARENT),
330 CLK_SET_RATE_PARENT),
351 __BIT(0), CLK_SET_RATE_PARENT),
353 __BIT(4), CLK_SET_RATE_PARENT),
355 __BIT(8), CLK_SET_RATE_PARENT),
364 __BIT(7), CLK_SET_RATE_PARENT),
366 __BIT(8), CLK_SET_RATE_PARENT),
368 __BIT(9), CLK_SET_RATE_PARENT),
370 __BIT(10), CLK_SET_RATE_PARENT),
[all...] |
| /src/sys/arch/arm/nxp/ |
| imx6_ccmvar.h | 256 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \
271 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \
288 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \
302 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \
|
| imx_ccm.c | 111 if (clkp->flags & CLK_SET_RATE_PARENT) {
133 if (clkp->flags & CLK_SET_RATE_PARENT) {
|
| imx_ccm.h | 95 .base.flags = CLK_SET_RATE_PARENT, \
244 .base.flags = CLK_SET_RATE_PARENT, \
|
| /src/sys/arch/riscv/starfive/ |
| jh71x0_clkc.h | 142 .flags = CLK_SET_RATE_PARENT, \
345 .flags = CLK_SET_RATE_PARENT, \
|
| jh7100_clkc.c | 223 JH71X0CLKC_MUX_FLAGS(JH7100_CLK_GMAC_TX, "gmac_tx", gmac_tx_parents, CLK_SET_RATE_PARENT),
|
| jh7110_clkc.c | 554 JH71X0CLKC_MUXGATE_FLAGS(JH7110_SYSCLK_GMAC1_TX, "gmac1_tx", gmac1_tx_parents, CLK_SET_RATE_PARENT), // CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
692 JH71X0CLKC_MUX_FLAGS(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", gmac0_rx_parents, CLK_SET_RATE_PARENT), // CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
|
| jh71x0_clkc.c | 543 if (clk->flags & CLK_SET_RATE_PARENT) {
|
| /src/sys/arch/arm/amlogic/ |
| meson_clk.c | 174 if (clkp->flags & CLK_SET_RATE_PARENT) {
196 if (clkp->flags & CLK_SET_RATE_PARENT) {
|
| meson_clk.h | 109 .base.flags = CLK_SET_RATE_PARENT, \
219 .base.flags = CLK_SET_RATE_PARENT, \
|
| /src/sys/arch/arm/sunxi/ |
| sunxi_ccu.c | 173 if (clkp->flags & CLK_SET_RATE_PARENT) {
195 if (clkp->flags & CLK_SET_RATE_PARENT) {
|
| sunxi_ccu.h | 85 .base.flags = CLK_SET_RATE_PARENT, \
435 .base.flags = CLK_SET_RATE_PARENT, \
|
| /src/sys/arch/arm/rockchip/ |
| rk_cru.c | 162 if (clkp->flags & CLK_SET_RATE_PARENT) {
185 if (clkp->flags & CLK_SET_RATE_PARENT) {
|
| rk_cru.h | 360 .base.flags = CLK_SET_RATE_PARENT, \
396 .base.flags = CLK_SET_RATE_PARENT, \
|
| /src/sys/arch/arm/ti/ |
| ti_prcm.c | 90 if (clkp->flags & CLK_SET_RATE_PARENT) {
|
| /src/sys/arch/arm/nvidia/ |
| tegra124_car.c | 344 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \
1432 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0);
|
| tegra210_car.c | 356 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \
1522 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0);
|
