Searched refs:CLK_TOP_APLL2_DIV0 (Results 1 - 3 of 3) sorted by relevance

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dmt8173-clk.h139 #define CLK_TOP_APLL2_DIV0 127 macro
H A Dmediatek,mt6795-clk.h134 #define CLK_TOP_APLL2_DIV0 121 macro
/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi870 <&topckgen CLK_TOP_APLL2_DIV0>,

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